4.5 Article

Synchronously Loaded Optical Packet Buffer

Journal

IEEE PHOTONICS TECHNOLOGY LETTERS
Volume 20, Issue 21-24, Pages 1757-1759

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LPT.2008.2004678

Keywords

Buffers; optical memories; optical switches; packet switching; synchronization

Funding

  1. DARPA/MTO
  2. ARL [W91 INF-04-9-0001]

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Synchronous optical packet buffering is demonstrated utilizing a fiber-based synchronizer with a photonic integrated circuit packet buffer. Asynchronously arriving packets are optically synchronized to a local frame clock and loaded synchronously into the optical buffer. The synchronizer is a flour-stage design with a resolution of 853 ps and a dynamic tuning range of 12.8 ns. The optical packet buffer consists or an integrated 2 x 2 InP switch coupled to a silica-on-silicon 12.8-ns delay line. Packet recovery measurements of 40-B return-to-zero packets at 40 Gb/s show-error free performance for several combinations of synchronizer and buffer delays.

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