Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

Title
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors
Authors
Keywords
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Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 47, Issue 3, Pages 744-756
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2012-02-23
DOI
10.1109/jssc.2011.2179451

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