Article
Computer Science, Information Systems
Jihyun Baek, Juyong Lee, Jintae Kim, Hyungil Chae
Summary: This paper presents a pipelined noise-shaping SAR ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter.
Article
Computer Science, Information Systems
Juyong Lee, Seungjun Lee, Kihyun Kim, Hyungil Chae
Summary: The study proposed a PLNS-SAR ADC structure with a ring amplifier to achieve high resolution, low power consumption, and noise suppression. With processing of residual signals and high-gain ring amplifier, a SNDR of 70 dB and a FoM(S)(,)(SNDR) of 163.5 dB were achieved in the implementation.
Article
Engineering, Electrical & Electronic
Hadi Pahlavanzadeh, Mohammad Azim Karami
Summary: A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The scheme reduces average switching energy and area and adopts a novel common-mode insensitive regenerative comparator to reduce non-linearity errors. The proposed ADC performs well in simulation with low power consumption and high effective number of bits.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2022)
Article
Engineering, Electrical & Electronic
Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun
Summary: This article presents a 12-bit 1-GS/s ADC with a hybrid architecture utilizing a pipelined and time-interleaved SAR. It uses backend time-interleaving to reduce power and design complexity, while eliminating sampling time skew. The architecture incorporates a ring amplifier (ring-amp) to reduce the power of residue amplification, and a PVT-robust ring-amp with split input is proposed to ensure performance under low supply voltage. A switched reference decoupling capacitor technique is also introduced to improve PSRR and reduce reference noise. The implemented ADC achieves a SNDR of 62.5 dB and a FoMS of 169.2 dB.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Engineering, Electrical & Electronic
Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
Summary: The pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure achieves high resolution and wide bandwidth while greatly relaxing the design requirements of each SAR quantizer, resulting in good power efficiency.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Chemistry, Physical
D. S. Shylu Sam, D. Jackuline Moni, P. Sam Paul, D. Nirmal
Summary: This work presents a low-power 10-bit 40 MSPS Pipelined ADC with high SFDR and SNDR achieved while consuming only 7.3mW power.
Article
Computer Science, Information Systems
Yimin Wu, Fan Ye, Junyan Ren
Summary: This paper presents a calibration-free, 16-channel, 14-bit ADC for ultrasound imaging systems. It achieves a high-performance and power-efficient design through reference sharing and optimized architecture. The ADC demonstrates competitive performance in ultrasound applications.
Article
Engineering, Electrical & Electronic
Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim
Summary: This paper introduces a new time-based pipelined ADC with MDAC stages capable of robust 2x residue amplification. The ADC does not require amplifiers, making it suitable for low-voltage digital processes. The prototype 10-bit ADC fabricated in 28nm CMOS demonstrates excellent performance with high FOM.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2021)
Article
Engineering, Electrical & Electronic
Hyunchul Yoon, Changuk Lee, Taewoong Kim, Yigi Kwon, Youngcheol Chae
Summary: This article introduces a PVT-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined SAR ADC. The proposed dynamic amplifier achieves a voltage gain of 16 and high linearity over a wide temperature range with an on-chip timing generator. The prototype ADC achieves a high SNDR and SFDR while consuming low power and showing minimal variations in SNDR.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Computer Science, Information Systems
Chong-Cheng Huang, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, Chao-Hung Huang
Summary: This paper presents a multichannel dual-mode SAR ADC designed for brushless DC motor drive, with advantages of low power consumption and high resolution achieved through the use of dual-mode sampling.
Article
Engineering, Electrical & Electronic
Haoyi Zhao, Fa Foster Dai
Summary: This article presents a power efficient and configurable pipelined SAR ADC that quantizes signals in both voltage and time domains to address PVT variations. The ADC utilizes a low-power SAR ADC as the coarse quantizer and a ring-configured TDC as the fine quantizer to improve linearity and power efficiency. The ADC prototype achieves high performance and consumes low power with a Nyquist input.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Engineering, Electrical & Electronic
Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
Summary: This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves high conversion speed and accuracy. With only two time-interleaved channels, the converter utilizes delay-tracking technique and selective delay-tuning unit to enhance performance. Experimental results show that the converter performs well in terms of signal-to-noise ratio and dynamic range, while also having a small active area.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2022)
Article
Engineering, Electrical & Electronic
Ali Pourahmad, Rasoul Dehghani, Seyed Amir-Reza Ahmadi-Mehr, Reza Lotfi
Summary: This study presents an innovative DAC-less SAR ADC architecture that uses a binary search algorithm to emulate the DAC function, overcoming the limitations of conventional DAC implementations. The hardware implementation of this architecture is less complex and more robust against PVT variations, while still being able to adapt to different sampling rates and resolutions.
MICROELECTRONICS JOURNAL
(2022)
Article
Computer Science, Information Systems
Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
Summary: This paper presents a 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC in 28-nm CMOS, utilizing a bias-enhanced ring amplifier, high linearity front-end design, and calibration techniques to achieve competitive performance at 250 MHz input frequency. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, with a FoM(w) of 0.48 pJ/conv.-step.
Article
Engineering, Electrical & Electronic
Xin Zhao, Dengquan Li, Xianghui Zhang, Shubin Liu, Zhangming Zhu
Summary: This work presents an ultralow-power ADC for implantable biosensor applications, featuring high energy efficiency, area efficiency, and low offset noise.
IEEE SENSORS JOURNAL
(2022)