A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Title
A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology
Authors
Keywords
-
Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 45, Issue 9, Pages 1896-1905
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2010-08-25
DOI
10.1109/jssc.2010.2053859

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