Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 45, Issue 5, Pages 1007-1015Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2010.2043893
Keywords
ADC; analog-to-digital converter; asynchronous; charge-redistribution; CMOS; comparators; DAC; digital-to-analog converter; dynamic power dissipation; figure of merit; low noise; low power; low static current; sense amplifiers; sensors; smart dust; step-wise charging; successive approximation; wireless sensor networks; wireless sensors
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This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115 x 225 mu m(2). At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 mu W and achieves an energy efficiency of 4.4 fJ/conversion-step.
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