Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

Title
Device Scaling Considerations for Nanophotonic CMOS Global Interconnects
Authors
Keywords
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Journal
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS
Volume 19, Issue 2, Pages 8200109-8200109
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2013-04-04
DOI
10.1109/jstqe.2013.2239262

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