Challenges and Directions for Low-Voltage SRAM

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

(2009) Mahmut E. Sinangil et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers

(2009) Stefan Cosemans et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

(2009) Joyce Kwong et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

(2008) Juergen Pille et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

(2008) Tae-Hyoung Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

(2008) Naveen Verma et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS