Karim Abozeid
Egypt The British University in Egypt
Published in 2016
- 8-bit 22nW SAR ADC using output offset cancellation technique
- Authors: Abozeid, K.M.; Aboudina, M.M.; Khalil, A.H.
- Journal: ICENCO 2015
- Description:
- In this paper we present an offset cancellation technique for a comparator used in SAR (successive approximation register) analog to digital converter improving the signal to noise ratio of the whole system with minimum power consumption at the expense of complexity of the system. An 8-bit SAR ADC is presented with power consumption 22nW, ENOB = 7.051 and SNR = 47.11 dB. All simulations are done under clock frequency = 100 kHz and a supply voltage 1V.
Published in 2015
- Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters
- Authors: Abozeid, K.M.; Aboudina, M.M.; Khalil, A.H.
- Journal: ICET 2014
- Description:
- This paper presents a comparison in the consumed power between different configurations of dynamic latched comparator used in low power Analog to Digital (A/D) converters especially the successive approximation register (SAR) which is used in many Electrical, Radio-frequency identification (RFID) and biomedical applications. This comparison is in architecture, consumed power and propagation time delay. The comparison is done under constant input referred offset.