A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

(2013) Amer Samarah et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$m CMOS

(2010) Seon-Kyoo Lee et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

(2010) Chia-Tsun Wu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

(2010) Xin Chen et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming

(2009) S. Mendel et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

A novel ADPLL design using successive approximation frequency control

(2009) H. Eisenreich et al.   MICROELECTRONICS JOURNAL

A low-power ADPLL using feedback DCO quarterly disabled in time domain

(2008) Chua-Chin Wang et al.   MICROELECTRONICS JOURNAL