A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

A Dither-Less All Digital PLL for Cellular Transmitters

(2012) Luca Vercesi et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

(2010) Jianjun Yu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

(2010) Takashi Tokairin et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

(2010) Enrico Temporiti et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Digital techniques for integrated frequency synthesizers: A tutorial

(2009) S. Pamarti   IEEE COMMUNICATIONS MAGAZINE

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

(2009) Ping-Ying Wang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping

(2009) Matthew Z. Straayer et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

(2008) Minjae Lee et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

(2008) Chun-Ming Hsu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Digital PLL With a Stochastic Time-to-Digital Converter

(2008) V. Kratyuk et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS