A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation

(2021) Jai-Ming Lin et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC

(2021) Jai-Ming Lin et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A graph placement methodology for fast chip design

(2021) Azalia Mirhoseini et al.   NATURE

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

(2021) Yi-Chen Lu et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning

(2021) Qi Xu et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits

(2020) Zongqing Ren et al.   IEEE Transactions on Components Packaging and Manufacturing Technology

A DEEP REINFORCEMENT LEARNING APPROACH FOR GLOBAL ROUTING

(2019) Haiguang Liao et al.   JOURNAL OF MECHANICAL DESIGN

Thermal and Wirelength Optimization With TSV Assignment for 3-D-IC

(2018) Yi Zhao et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs

(2017) Jai-Ming Lin et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment

(2017) Cong HAO et al.   IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUT

Fast thermal analysis for fixed-outline 3D floorplanning

(2017) Qi Xu et al.   INTEGRATION-THE VLSI JOURNAL

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment

(2017) Cong HAO et al.   IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES

Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning

(2016) Qi Xu et al.   APPLIED SOFT COMPUTING

Planning Massive Interconnects in 3-D Chips

(2015) Johann Knechtel et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices

(2014) Amirkoushyar Ziabari et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits

(2013) Yibo Chen et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Integrated Algorithm for 3-D IC Through-Silicon Via Assignment

(2013) Xiaodong Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement

(2012) Cha-Ru Li et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Through-Silicon Via Planning in 3-D Floorplanning

(2010) Ming-Chao Tsai et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

(2008) Tung-Chieh Chen et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS