期刊
MICROELECTRONICS RELIABILITY
卷 52, 期 11, 页码 2851-2855出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.microrel.2012.05.007
关键词
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Flip-chip packages with a 40 nm wafer node with ELK (extreme low-k) dielectric are prone to early low-k delamination beneath the solder joints right upon flip-chip bonding before underfilling. The chip-package interaction (CPI) therefore becomes a design consideration for flip-chip packages with a 40 nm wafer node and beyond. In this work, finite element analyses were carried out to explore CPI in process of a 40 nm ELK flip-chip package with SnAg solder joints. Results indicate that a small ratio of polyimide (PI) opening over under bump metallurgy (UBM) size, a thick redistribution layer (RDL) or RDL sandwiched with PI for stress buffering, a thick substrate core, and a thin die are directions to follow in order to minimize the ELK delamination potential. (C) 2012 Elsevier Ltd. All rights reserved.
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