Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

(2009) Y.K. Chin et al.   IEEE ELECTRON DEVICE LETTERS

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

(2009) Peng-Fei Guo et al.   IEEE ELECTRON DEVICE LETTERS

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

(2009) Z.X. Chen et al.   IEEE ELECTRON DEVICE LETTERS

Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

(2009) Yasin Khatami et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Enhanced carrier injection in Schottky contacts using dopant segregation: a Monte Carlo research

(2009) Elena Pascual et al.   SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates

(2008) Anne S. Verhulst et al.   IEEE ELECTRON DEVICE LETTERS

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

(2008) Osama M. Nayfeh et al.   IEEE ELECTRON DEVICE LETTERS

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

(2008) B. Yang et al.   IEEE ELECTRON DEVICE LETTERS

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

(2008) Navab Singh et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES