Article
Engineering, Electrical & Electronic
Jae Seong Lee, Woo Young Choi
Summary: The proposed tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) introduces a single nanoelectromechanical (NEM) memory switch replacing two static random access memory cells, resulting in significant improvements in area, power consumption, search speed, and static leakage current compared to traditional TCAM.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Computer Science, Information Systems
Hyunju Kim, Mannhee Cho, Sanghyun Lee, Hyug Su Kwon, Woo Young Choi, Youngmin Kim
Summary: Content-addressable memory (CAM) conducts a parallel search operation by comparing search data with all content stored in memory in a single cycle, rather than using an address. This paper introduces a static-based architecture for low-power, high-speed BCAM and TCAM, utilizing NEM memory switch for nonvolatile data storage. The proposed CAM design shows significant improvements in propagation delay, matching power, and area compared to conventional designs.
Article
Computer Science, Information Systems
Jae Seong Lee, Woo Young Choi
Summary: The paper introduces a novel nanoelectromechanical-switch-based binary content-addressable memory (NEMBCAM) for the first time, which achieves a smaller unit cell area and reduced search energy consumption through monolithic three-dimensional integration. The near-perfect on/off characteristic of the NEM memory switch also leads to a shorter search delay.
Article
Engineering, Electrical & Electronic
Sumit Saha, Arpit Singh, Maryam Shojaei Baghini, Mayank Goel, V. Ramgopal Rao
Summary: In this article, a double-clamped nano-electromechanical switch (NEMS) with low stand-by power is proposed as an effective solution to leakage issues in scaled CMOS-based power gating (PG) in logic circuits. The NEMS structure achieves low pull-in voltage, low hysteresis, low turn-on delay, and subthreshold slope, enabling reduction in stand-by power dissipation in sub 10-nm CMOS technologies. Experimental results demonstrate significant leakage energy reduction compared to sub 10-nm CMOS based PG in ISCAS'85 benchmark circuits.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Lars Prospero Tatum, Urmita Sikder, Tsu-Jae King Liu
Summary: Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. It is found that sub-20-ns programming delay is possible with programming voltages compatible with standard input-output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is effective for avoiding write disturbance.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
Summary: FPGAs offer low latency, high energy efficiency, and flexibility, but traditional SRAM FPGAs have challenges like high standby power and low logic density. Researchers have introduced emerging NV memory technologies to address standby power issues in FPGAs.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2022)
Article
Multidisciplinary Sciences
Kaichen Zhu, Sebastian Pazos, Fernando Aguirre, Yaqing Shen, Yue Yuan, Wenwen Zheng, Osamah Alharbi, Marco A. Villena, Bin Fang, Xinyi Li, Alessandro Milozzi, Matteo Farronato, Miguel Munoz-Rojo, Tao Wang, Ren Li, Hossein Fariborzi, Juan B. Roldan, Guenther Benstetter, Xixiang Zhang, Husam N. Alshareef, Tibor Grasser, Huaqiang Wu, Daniele Ielmini, Mario Lanza
Summary: In this study, high-integration-density 2D-CMOS hybrid microchips for memristive applications were fabricated, with CMOS transistors providing excellent control over hexagonal boron nitride memristors. Logic gates were constructed, and spike-timing dependent plasticity signals suitable for spiking neural networks were measured.
Article
Engineering, Electrical & Electronic
Jinsong Cui, Fufei An, Jiangchao Qian, Yuxuan Wu, Luke L. Sloan, Saran Pidaparthy, Jian-Min Zuo, Qing Cao
Summary: Oxide-based solid-state protonic electrochemical transistors can operate by transferring protons between a hydrogenated tungsten oxide channel and gate through a zirconium dioxide protonic electrolyte. These devices offer multistate and symmetric programming of channel conductance via gate-voltage pulse control and have small cycle-to-cycle variation. They can be programmed at frequencies approaching the megahertz range and exhibit enduring performance. Through monolithic integration with silicon transistors, they can be used to create efficient deep learning accelerator applications.
NATURE ELECTRONICS
(2023)
Article
Chemistry, Multidisciplinary
Jin-Fa Chang, Yo-Sheng Lin
Summary: The paper presents a low-loss, high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications, achieving optimized insertion loss and isolation levels across different frequency bands through the use of traveling-wave matching and pi-matching. At 28 GHz, the switch achieved one of the best IP1dB results ever reported in the millimeter-wave range.
APPLIED SCIENCES-BASEL
(2021)
Article
Multidisciplinary Sciences
Jiabin Shen, Shujing Jia, Nannan Shi, Qingqin Ge, Tamihiro Gotoh, Shilong Lv, Qi Liu, Richard Dronskowski, Stephen R. Elliott, Zhitang Song, Min Zhu
Summary: The research introduces a single-element tellurium (Te) volatile switch with high drive current density, large ON/OFF current ratio, and fast switching speed, which may help realize denser memory chips.
Article
Engineering, Electrical & Electronic
Hyug Su Kwon, Woo Young Choi
Summary: Research on NEM devices for logic and memory applications has been reviewed in the context of monolithic 3D (M3D) heterogeneous integration. The backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are detailed, and 65-nm process based M3D CMOS-NEM RL circuits are proposed. It is predicted that these proposed circuits will exhibit significantly higher chip density, operation frequency, and lower power consumption compared to CMOS-only circuits in tile-to-tile operation.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
(2022)
Article
Engineering, Electrical & Electronic
Minsik Park, Jonghyun Song, Jaeyong Jeong, Jeong-Taek Lim, Jae-Hyeok Song, Won-Chul Lee, Gapseop Sim, Huijae Cho, Dongeun Yoo, Minho Kang, Hyoungho Ko, Jooseok Lee, Kyounghoon Yang, Choul-Young Kim, Youngsu Kim, Woo-Suk Sul, Sanghyeon Kim, Jongwon Lee
Summary: In this article, a simple 200-mm Si CMOS process-based integrated passive device (IPD) stack for millimeter-wave (mmW) monolithic 3-D (M3D) integration is introduced. By developing a double chemical mechanical polishing (CMP) technique for the final intermetal dielectric (IMD) process, a uniform 3-D integration of a 100-nm-thick active layer of the InGaAs high-electron-mobility transistor (HEMT) was achieved. The fabricated passive devices showed good quality factor (Q) characteristics sufficient to be utilized up to the V-band, with the inductors having the highest Q values among Si lumped inductors in mmW bands reported so far.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Multidisciplinary Sciences
Mingyi Rao, Hao Tang, Jiangbin Wu, Wenhao Song, Max Zhang, Wenbo Yin, Ye Zhuo, Fatemeh Kiani, Benjamin Chen, Xiangqi Jiang, Hefei Liu, Hung-Yu Chen, Rivu Midya, Fan Ye, Hao Jiang, Zhongrui Wang, Mingche Wu, Miao Hu, Han Wang, Qiangfei Xia, Ning Ge, Ju Li, J. Joshua Yang
Summary: Neural networks based on memristive devices have the potential to improve throughput and energy efficiency in machine learning and artificial intelligence, especially in edge applications. To commercialize edge applications, it is practical to download synaptic weights from cloud training and program them into memristors. High-precision programmability is required for memristors in neural network applications to ensure uniform and accurate performance across multiple networks.
Article
Engineering, Electrical & Electronic
Zhaoxing Qin, Kazunori Kuribara, Yasuhiro Ogasahara, Takashi Sato
Summary: This paper presents a novel SRAM based on low-voltage organic thin-film transistors for local data storage and signal post-processing in flexible electronic systems. The proposed circuit combines CMOS and pseudo-CMOS designs for improved stability and area efficiency. The degradation-mitigation circuit extends retention time and can automatically detect and mitigate device degradation.
IEEE SENSORS JOURNAL
(2023)
Article
Engineering, Electrical & Electronic
Hoonhee Han, Hyeon Cheol Cho, Seok Min Jang, Changhwan Choi
Summary: A thin Si layer transfer process for monolithic 3D (M3D) integration using H+ implantation is proposed, and the photosensor and ring oscillator circuits of the M3D system are demonstrated. Compared with the continuous device scaling approach, M3D may be an alternative scheme for low-power, high-performance, and multi-functional devices.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Jae Seong Lee, Jisoo Yoon, Woo Young Choi
Summary: In this study, a nano-electromechanical-switch-based ternary content-addressable memory (NEMTCAM) is introduced for nearest neighbor (NN) classifier to overcome the bottleneck in conventional NN search architecture. NEMTCAM can perform parallel search operations to compute Hamming distance between input and stored vectors. Experimental demonstrations of NEMTCAM operation are provided, and an analytical model is presented to evaluate NN search accuracy, considering cell-to-cell parasitic resistance.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Jisoo Yoon, Hyug Su Kwon, Woo Young Choi
Summary: In this study, monolithic three-dimensional (M3D) multilayer nanoelectromechanical (NEM) memory switches were experimentally demonstrated for reconfigurable multi-path routing. The multi-layer NEM memory switch has moving mechanical beams in different metal layers, operating independently and nonvolatilely, including high impedance states. It is predicted that n-layer NEM memory switches utilizing n metal layers will exhibit 3((n-1)) x higher routing flexibility and nx higher chip density than conventional single-layer NEM memory switches.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Computer Science, Information Systems
Hyunju Kim, Mannhee Cho, Sanghyun Lee, Hyug Su Kwon, Woo Young Choi, Youngmin Kim
Summary: Content-addressable memory (CAM) conducts a parallel search operation by comparing search data with all content stored in memory in a single cycle, rather than using an address. This paper introduces a static-based architecture for low-power, high-speed BCAM and TCAM, utilizing NEM memory switch for nonvolatile data storage. The proposed CAM design shows significant improvements in propagation delay, matching power, and area compared to conventional designs.
Article
Engineering, Electrical & Electronic
Jin Ho Chang, Ji Ho Uhm, Hyug Su Kwon, Eunmee Kwon, Woo Young Choi
Summary: The influence of CHRR on HC VNAND flash memory was investigated and a recessed channel HC VNAND flash memory cell was proposed to address the issues.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Tae-Hyeon Kim, Kyungho Hong, Sungjoon Kim, Jinwoo Park, Sangwook Youn, Jong-Ho Lee, Byung-Gook Park, Hyungjin Kim, Woo Young Choi
Summary: In this study, a fuse device was developed for hardware neural network pruning. The device was characterized in a 1F1R structure and achieved a blow time of 0.4 µs and read endurance of >10^7. A fuse design method was also developed to adjust blow voltage and current, enabling the fuse to be used in various synaptic devices. Simulation results demonstrated the performance improvement achieved by disconnecting defective devices through fuse operations during network pruning.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Kyu-Ho Lee, Dongseok Kwon, Sung Yun Woo, Jong Hyun Ko, Woo Young Choi, Byung-Gook Park, Jong-Ho Lee
Summary: In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). The SPB exhibits a highly linear relationship between the current sum and the output spike frequency, enabling precise mimicry of artificial neural networks with ReLU activation function. A single layer SNN is experimentally demonstrated for classifying digit patterns.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Computer Science, Hardware & Architecture
Junmo Lee, Joon Hwang, Youngwoon Cho, Min-Kyu Park, Woo Young Choi, Sangbum Kim, Jong-Ho Lee
Summary: This article introduces a hardware-efficient on-chip weight update scheme called CRUS, which algorithmically mitigates the nonlinear weight update in synaptic devices. By introducing the update noise (UN) metric and adjusting the LTD skip conditions, CRUS achieves over 90% accuracy on the MNIST dataset and exhibits robustness to cycle-to-cycle variations.
IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS
(2022)
Article
Engineering, Electrical & Electronic
Ji Ho Uhm, Jin Ho Chang, Joonggyu Kim, Eunmee Kwon, Woo Young Choi
Summary: The reliability issues of the hemi-cylindrical (HC) vertical NAND (VNAND) flash memory were investigated with various channel hole remaining ratios (CHRRs). The nonuniform injection of carriers to the charge-trapping layer during program/erase operations in the case of HC VNAND was observed. A novel charge redistribution mechanism called azimuthal redistribution (AR) was proposed in addition to the conventional lateral migration. Simulation and experimental results showed that AR played a significant role in the data retention of HC VNAND cells as a function of the CHRR.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Taejin Jang, Bosung Jeon, Seunghwan Song, Woo Young Choi
Summary: A poly-Si overpass channel synaptic (OCS) transistor is proposed for low-power operation and low RC delay in neuromorphic systems. The OCS transistor has advantages in reducing on-current to sub 100 nA with high on/off ratio and finely dividing synaptic weights. Experimental demonstrations show the suitability of the OCS array for vector-matrix multiplication (VMM) operation and the adjustment of synaptic weights in sub-nA resolution. Classification accuracy of the fashion MNIST dataset remains high even after one year with four-bit quantization of spiking neural network (SNN).
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Jangsaeng Kim, Young-Tak Seo, Wonjun Shin, Woo Young Choi, Byung-Gook Park, Jong-Ho Lee
Summary: In this study, we propose an efficient exploration method using the low-frequency noise of synaptic devices, which is applicable to hardware-based deep Q-networks. The proposed method achieves exploration efficiently with a relatively low hardware burden compared to other published studies. A rounded dual-channel flash memory cell is utilized as the synaptic device. The performance evaluation based on a simple Snake game demonstrates that the proposed system achieves similar performance to that using the epsilon-greedy exploration method, even with a low noise level of the synaptic devices and without the need for an additional circuit.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Automation & Control Systems
Jae Seung Woo, Chae Lin Jung, Ki Ryung Nam, Woo Young Choi
Summary: This study experimentally demonstrates the potential of charge-trapping tunnel field effect transistors (CT-TFETs) for energy-efficient large-scale neuromorphic arrays. Compared to CT-MOSFET arrays, CT-TFET arrays exhibit higher accuracy, lower power consumption, and stronger immunity against voltage (IR) drops, making them suitable for large-scale neuromorphic applications.
ADVANCED INTELLIGENT SYSTEMS
(2023)
Article
Computer Science, Information Systems
Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, Woo Young Choi
Summary: The snapback breakdown behavior of multi-finger MOSFETs was studied using device simulation. It was found that the snapback breakdown voltage (SNBV) varies depending on the source/drain configuration, even with the same two-finger structure. This variation is attributed to hole current crowding beneath the shared source, which increases forward biasing at the source-substrate junction and prematurely activates the parasitic bipolar junction transistor (BJT). Double-pocket implantation successfully suppresses hole current crowding and achieves higher SNBV for two-finger MOSFETs.
Article
Computer Science, Information Systems
Ki Ryung Nam, Kwang Soo Kim, Woo Young Choi
Summary: The effects of low net-doped region on the electrical performance of tunnel field-effect transistors (TFETs) were investigated using a TCAD simulation. The low net-doped region between the source and pocket was found to enhance TFET electrical characteristics, such as the on-current (I-on) and subthreshold swing (SS), with a fine on-off current ratio (I-on/I-off). By optimizing the length of the low net-doped region, I-on increased 14.6 times and SS was reduced by 34.6% compared to TFETs without the low net-doped region. Guidelines for designing counter-doped pocket considering the low net-doped region were proposed.
Article
Computer Science, Information Systems
Jae Seung Woo, Jang Woo Lee, Woo Young Choi
Summary: The hot carrier injection (HCI) of tunnel field-effect transistors (TFETs) is quantitatively analyzed for the first time in terms of HCI-induced gate current, HCI probability, potential energy, and lateral/vertical electric field. The TFETs show higher HCI probability than MOSFETs under all bias conditions due to the strong peak lateral field at the source-channel junction. The optimal HCI bias condition of TFETs is also examined.
Article
Engineering, Electrical & Electronic
Jang Woo Lee, Jae Seung Woo, Woo Young Choi
Summary: This article demonstrates the experimental realization of a synaptic cell composed of two TFETs capable of performing XNOR operation in binary neural networks. The proposed synaptic TFETs exhibit lower current during inference and higher programming efficiency during weight transfer compared to conventional synaptic transistors. Additionally, the fabricated synaptic TFET arrays meet the energy requirement and have a low bit-error rate.
IEEE ELECTRON DEVICE LETTERS
(2022)