Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

Thin-dielectric-layer engineering for 3D nanostructure integration using an innovative planarization approach

(2015) Y Guerfi et al.   NANOTECHNOLOGY

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate

(2014) Yujia Zhai et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

(2013) N. Clément et al.   APPLIED PHYSICS LETTERS

High resolution HSQ nanopillar arrays with low energy electron beam lithography

(2013) Y. Guerfi et al.   MICROELECTRONIC ENGINEERING

Vertical nanowire array-based field effect transistors for ultimate scaling

(2013) G. Larrieu et al.   Nanoscale

A III–V nanowire channel on silicon for high-performance vertical transistors

(2012) Katsuhiro Tomioka et al.   NATURE

Carrier injection at silicide/silicon interfaces in nanowire based-nanocontacts

(2012) X.-L. Han et al.   SURFACE SCIENCE

CMOS Inverter Based on Schottky Source–Drain MOS Technology With Low-Temperature Dopant Segregation

(2011) Guilhem Larrieu et al.   IEEE ELECTRON DEVICE LETTERS

Realization of ultra dense arrays of vertical silicon nanowires with defect free surface and perfect anisotropy using a top-down approach

(2011) Xiang-Lei Han et al.   MICROELECTRONIC ENGINEERING

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

(2011) Isabelle Ferain et al.   NATURE

Simulation of junctionless Si nanowire transistors with 3 nm gate length

(2010) Lida Ansari et al.   APPLIED PHYSICS LETTERS

Realization of Vertical Silicon Nanowire Networks with an Ultra High Density Using a Top–Down Approach

(2010) Xiang-Lei Han et al.   JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY

Nanowire transistors without junctions

(2010) Jean-Pierre Colinge et al.   Nature Nanotechnology

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

(2008) B. Yang et al.   IEEE ELECTRON DEVICE LETTERS

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

(2008) C. Thelander et al.   IEEE ELECTRON DEVICE LETTERS