期刊
NANOSCALE
卷 5, 期 6, 页码 2437-2441出版社
ROYAL SOC CHEMISTRY
DOI: 10.1039/c3nr33738c
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资金
- European Commission through the NANOSIL Network of Excellence [FP7-IST-216171]
- European Commission through the NANO-TEC [FP7-257694]
- French RENATECH network (French national nanofabrication platform)
Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in ultimate transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.
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