3-D NAND Technology Achievements and Future Scaling Perspectives

Since the introduction of a 3-D NAND product in 2014, the areal density has increased by more than 8 times (from 0.96 to 7.80 Gb/mm(2)) in the recent five years. The increase of word-line (WL) stacking from 24 to 128 layers, the scaling of bits per cell from 2 to 3 bits/cell and 4 bits/cell, and a CMOS under array technology enabled this successful 3-D NAND density scaling. A gate-all-around cell architecture realized excellent reliability and program/read performance by having a large physical cell size and good shielding of cell-to-cell interference. In the newly introduced 3-D NAND devices, several new cell phenomena have been reported. Unique temperature dependence and threshold-voltage instability are observed due to the polysilicon channel. Down-coupling of the floating body and its impact on program disturb and hot electron injection were reported. The cell-to-cell interference is enhanced by the effective gate length modulation due to the no-lightly doped drain (LDD) string architecture. For the future 3-D NAND scaling, WL stacking will continue to be a key driver. In addition, XYZ dimension shrink of the cell will become another key critical scaling direction in order to relieve the cost and device challenges introduced by the WL stacking. Various device and structure solutions for the XYZ cell scaling have been suggested. The good engineering in number of electrons and cell-to-cell interference in the XYZ scaled cell will be critical in order to maintain the excellent reliability and performance of 3-D NAND.