4.8 Article

Double Negative Differential Transconductance Characteristic: From Device to Circuit Application toward Quaternary Inverter

期刊

ADVANCED FUNCTIONAL MATERIALS
卷 29, 期 48, 页码 -

出版社

WILEY-V C H VERLAG GMBH
DOI: 10.1002/adfm.201905540

关键词

2D heterojunction; graphene; multivalued logic; negative differential transconductance; van der Waals material; vdW heterojunction; WS2; WSe2

资金

  1. National Research Foundation of Korea (NRF) - Korea government (MSIP) [2018R1A2A2A05020475, 2017R1A4A1015400, 2016M3A7B4910426]
  2. Ministry of Trade, Industry and Energy (MOTIE) [10067739]
  3. Korea Semiconductor Research Consortium (KSRC)
  4. National Research Foundation of Korea [2018R1A2A2A05020475, 2017R1A4A1015400, 2016M3A7B4910426] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

向作者/读者索取更多资源

Multi-valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming big data era. The feasibility of MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS2-graphene-WSe2 van der Waals heterostructure is evolved to a double-NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double-NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature-dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double-peak NDT device and a p-channel transistor through Cadence circuit simulation is theoretically demonstrated.

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