A cost-efficient error-resilient approach to distributed arithmetic for signal processing

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperature variations. The proposed approach mitigates the effect of timing violations by first providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the order of DA serial operations and borrowing time from the least significant bit (ISB) group. Therefore, LSB computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Moreover, the shifted-phase clock signals are applied on the end-point registers, thereby increasing the global guardband without any effect on system sampling rate. Our approach is demonstrated on a 16-tap FIR filter using the 65 nm CMOS process. The simulation results demonstrate that this design can maintain error-free operation without worst case timing margin, and achieve up to 42% power savings by voltage scaling when the worst case margin is considered. This is at the cost of a 6.3% delay and 7.3% overhead.