A low-jitter all-digital PLL with high-linearity DCO

Mono-component AM–FM Signal Decomposition Based on Discrete Second-Order Generalized Integrator Phase-Locked Loop

(2016) Aby K. George et al.   CIRCUITS SYSTEMS AND SIGNAL PROCESSING

Near-threshold all-digital PLL with dynamic voltage scaling power management

(2016) C.-W. Chang et al.   ELECTRONICS LETTERS

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

(2016) Ching-Che Chung et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

(2015) Mitsuhiko Igarashi et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

(2015) Chang-Hyeon Lee et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices

(2012) Wu-Hsin Chen et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

(2009) Hsuan-Jung Hsu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

(2008) Minjae Lee et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS