A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

标题
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
作者
关键词
-
出版物
出版商
Institute of Electrical and Electronics Engineers (IEEE)
发表日期
2009-10-14
DOI
10.1109/tvlsi.2009.2030410

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