Degradation of vertical GaN-on-GaN fin transistors: Step-stress and constant voltage experiments

We present an extensive analysis of the degradation of GaN-on-GaN fin-vertical transistors submitted to stress under positive gate voltage and off-state conditions. By analysing the degradation kinetics we demonstrate the existence of different processes: (i) trapping of electrons in the gate insulator under positive gate bias, (ii) time dependent breakdown of the gate MOS structure under forward gate voltage; (iii) catastrophic failure for off state voltages higher than 280 V. 2D simulations are used to identify the physical location of the failed region, and to investigate the dependence of electric field on fin width (values between 70 nm, 195 rim and 280 nm).