期刊
MICROELECTRONICS RELIABILITY
卷 52, 期 3, 页码 530-533出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.microrel.2011.10.016
关键词
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资金
- Office of Science, Office of Basic Energy Sciences, Materials Sciences Division, of the US Department of Energy at Lawrence Berkeley National Laboratory and University of California, Berkeley, California [DE-AC02-05CH11231]
- NSF [0416243]
- Los Alamos National Laboratory (LANL) [LDRD/X93V]
- Ministry of Knowledge Economy, Korea
Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234 MPa in the as-fabricated state, to -196 MPa (compressive) during thermal annealing (in situ measurement), to 167 MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17 mu m. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns. (C) 2011 Elsevier Ltd. All rights reserved.
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