期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 61, 期 2, 页码 533-539出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2013.2294831
关键词
3-D integration; alignment; microbump; self-assembly; wafer-level processing; water surface tension
资金
- Global Integration Initiative and Jun-Ichi Nishizawa Research Center with Tohoku University
- Japan Society for the Promotion of Science [21226009]
- Sumitomo Bakelite Company, Ltd.
- DISCO Inc.
- Grants-in-Aid for Scientific Research [21226009] Funding Source: KAKEN
A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 mu m when 3 x 3-, 5 x 5-, 4 x 9,- or 10 x 10-mm(2) chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-mu m-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of similar to 40 m Omega/bump was sufficiently low for 3-D large-scale integration application.
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