Wafer-Level Integration of High-Quality Bulk Piezoelectric Ceramics on Silicon

In this paper, we present a new post-CMOS-compatible piezoelectric thin/thick film technology that allows wafer-level integration of bulk piezoelectric ceramics such as lead zirconium titanate (PZT) and lead magnesium niobatelead titanate (PMN-PT) on silicon substrates with precisely determined final film thickness of 5-100 mu m while preserving the original material quality. We bond commercially available bulk piezoelectric substrates to silicon using reliable and low-temperature (200 degrees C) gold-indium (Au-In) diffusion bonding or parylene bonding. An enhanced fixed-abrasive lapping/polishing process thins the piezoelectric layer to the desired thickness with high precision and wafer-level uniformity (+/- 0.5 mu m). The fabricated films have bond interface shear strength of 1.5-4.5 MPa and average surface roughness of 43 nm, with bulk ferroelectric/piezoelectric properties preserved, such as remnant polarization (37.7 mu C/cm(2)), coercive field (1.95 kV/mm), and effective longitudinal piezoelectric strain coefficients (140-840 pm/V). In addition, extensions of this process show the feasibility of fabricating bimorph layers via successive bonding/thinning, and of forming suspended structures on silicon via surface micromachining. The flexible process can easily be adapted for batch-mode silicon integration of a variety of other electroceramics.