Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors

We propose an extraction technique for parasitic resistance (R-P) with L-, V-GS-, and V-DS-dependences even for large V-DS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing I-DS-V-GS characteristics (as a function of V-DS) of two a-IGZO TFTs with different channel lengths (L-1 and L-2). The resistance between the source and drain is modeled as an effective total resistance defined as R-T* = V-DS/I-D for all over the drain bias V-DS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the parasitic resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (V-DS') is accurately calculated as a function of V-GS, V-DS, and L by deembedding the voltage drop across the parasitic resistance R-P.