Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

标题
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
作者
关键词
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出版商
Institute of Electrical and Electronics Engineers (IEEE)
发表日期
2017-11-09
DOI
10.1109/jetcas.2017.2771529

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