An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform

(2014) Xiaoqiang Zhang et al.   IEICE Electronics Express

A low-cost UHF RFID tag chip with AES cryptography engine

(2013) Lingzhi Fu et al.   Security and Communication Networks

Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

(2011) M. M. Wong et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Composite field GF(((22)2)2) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion

(2011) M.M. Wong et al.   IET Circuits Devices & Systems

Effect of glitches against masked AES S-box implementation and countermeasure

(2009) M. Alam et al.   IET Information Security

Energy-efficient and security-optimized AES hardware design for ubiquitous computing

(2008) Chen Yicheng et al.   Journal of Systems Engineering and Electronics