Article
Nanoscience & Nanotechnology
Sangho Lee, Yongsun Lee, Taeho Kim, Giuk Kim, Taehyong Eom, Hunbeom Shin, Yeongseok Jeong, Sanghun Jeon
Summary: To stabilize the negative capacitance effect, the dielectric must be integrated into a heterostructure with a ferroelectric film. However, in multidomain hafnia, the charge boosting effect is reduced due to a lowering of the depolarization field at each domain, and operating voltage increases due to voltage division at the dielectric.
ACS APPLIED MATERIALS & INTERFACES
(2022)
Article
Engineering, Electrical & Electronic
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Summary: This paper introduces an undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET) with a low operating voltage (0.5 V) and compares its DC and RF performance parameters with those of the conventional charge plasma-based symmetrical gate electron-hole bilayer TFET (CP-SG-EHBTFET). The proposed UV-DBL-TFET utilizes a charge plasma technique to induce source/drain and electron-hole dual-bilayer channel dopants, resulting in a simple and efficient fabrication process without the need for thermal annealing. Compared to the CP-SG-EHBTFET, the UV-DBL-TFET demonstrates a dual EHB channel, dual line tunnelling, and improved ON current and RF/analog performance.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
(2023)
Article
Chemistry, Multidisciplinary
Juan Lyu, Jian Gong
Summary: It has been discovered that a two-dimensional semiconductor-semiconductor combination can also be used as an efficient cold source, as verified by computer simulation. By interfacing with n-doped HfS2, MoTe2 can be p-type-doped, reducing the subthreshold swing and enhancing the on-state current. A hybrid transport mechanism involving cold injection and tunneling effect is found in this p- and n-type HfS2/MoTe2 FET.
Article
Engineering, Electrical & Electronic
Hyun Woo Kim, Daewoong Kwon
Summary: The L-shaped tunnel FET introduced in this work, engineered with pocket doping, demonstrates improved performance by suppressing corner tunneling and enhancing on/off transition. Through optimized pocket doping concentration, the subthreshold swing is reduced and the on-current is significantly increased compared to conventional L-shaped TFETs, even in devices with extremely scaled gate length.
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
(2021)
Article
Materials Science, Multidisciplinary
Minhaz Uddin Sohag, Md Sherajul Islam, Kamal Hosen, Md Al Imran Fahim, Md Mosarof Hossain Sarkar, Jeongwon Park
Summary: A dual-source vertical tunnel field-effect transistor (TFET) with GaSb/InGaAsSb/InAs heterostructure is proposed, incorporating the negative capacitance effect to greatly enhance device performance and reduce energy consumption.
RESULTS IN PHYSICS
(2021)
Article
Nanoscience & Nanotechnology
Wei Li, Qingrui Jia, Yumei Pan, Xi'an Chen, Yue Yin, Yupan Wu, Yucheng Wang, Yi Wen, Chao Wang, Shaoxi Wang
Summary: This study proposed a novel T-shaped gate TFET based on silicon with ferroelectric material, NC-TGTFET, which exhibits a steep subthreshold swing and high on-state current. Analysis using simulation tools explored the influences of thickness, doping concentration, and ferroelectric material properties on the characteristics of NC-TGTFET.
Article
Nanoscience & Nanotechnology
Hui Quan, Dehuan Meng, Xuezhou Ma, Chenguang Qiu
Summary: This study demonstrates a MoS2 NC FET with a CuInP2S6 ferroelectric, which exhibits a large on/off ratio, a steep subthreshold swing, and a wide drain current range. By inserting an h-phase boron nitride layer, the hysteresis is reduced and ideal switching behavior is achieved.
ACS APPLIED MATERIALS & INTERFACES
(2023)
Article
Computer Science, Information Systems
Puneet Kumar Mishra, Amrita Rai, Nitin Sharma, Kanika Sharma, Nitin Mittal, Mohd Anul Haq, Ilyas Khan, ElSayed M. Tag El Din
Summary: This research work focuses on the fundamental advantages of carbon-based graphene material, such as high tunnelling probability, symmetric band structure, low effective mass, and characteristics of its 2D atomic layers. The impact of various factors on Graphene-based Tunnel Field Effect Transistor (TFET) is analyzed using simulation, including channel thickness, gate under-lap, doping method, workfunction of gate contact, and High-K material. The simulation results show significant improvement in subthreshold swing, Ion/Ioff ratio, and threshold voltage of the TFET, making it suitable for low power digital applications with a power supply of 0.5 V.
CMC-COMPUTERS MATERIALS & CONTINUA
(2023)
Article
Chemistry, Physical
Chin-Sheng Pang, Shu-Jen Han, Zhihong Chen
Summary: TFETs have emerged as a potential candidate to outperform conventional FETs at low voltages, with their operation mechanism overcoming the fundamental subthreshold swing limit. CNT-based TFETs show excellent performance with a minimum SS of 41 mV/dec and nearly no temperature dependence, paving a promising path for low-power electronic applications. TFET devices using CNTs with smaller bandgaps exhibit a record high BTBT current, indicating potential for high performance electronic applications.
Article
Engineering, Electrical & Electronic
Sadegh Kamaei, Xia Liu, Ali Saeidi, Yingfen Wei, Carlotta Gastaldi, Juergen Brugger, Adrian M. Ionescu
Summary: The integration of logic switches and neuromorphic functions using 2D semiconductors and ferroelectric materials on the same platform is demonstrated. Four types of logic switches and artificial synapses are created, showcasing their potential for low power computing and novel functionalities.
NATURE ELECTRONICS
(2023)
Article
Engineering, Electrical & Electronic
Aadil Anam, Naveen Kumar, S. Intekhab Amin, Dinesh Prasad, Sunny Anand
Summary: This paper introduces a complementary charge-plasma based symmetrical-gate electron-hole bilayer tunnel field-effect transistor (TFET) that operates at a low voltage (<= 0.5 V). The source/drain and EHB-channel are induced using the CP technique by depositing a metal electrode with the appropriate work function. The proposed EHB-TFET offers immunity against random dopant fluctuations and the feasibility of a self-aligned process, making it a reliable and efficient device for fabrication.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
(2023)
Article
Computer Science, Hardware & Architecture
Naima Guenifi, Shiromani Balmukund Rahi, Faiza Benmahdi, Houda Chabane
Summary: This paper proposes a method to improve the performance of tunnel field effect transistors (TFETs) by using barium titanate (BaTiO3) as a ferroelectric material in the source region instead of high-kappa dielectric HfO2. The replacement of HfO2 by BaTiO3 significantly enhances the ON-state current (I-ON), while the OFF-state current (I-OFF) remains unaffected. The study compares the performance of TFET structures based on high-kappa and ferroelectric materials, and shows the advantage of the ferroelectric structure. Parametric analysis and optimization using the genetic algorithm AG are conducted to further improve the I-ON current without affecting I-OFF.
JOURNAL OF SUPERCOMPUTING
(2023)
Article
Nanoscience & Nanotechnology
Qianwen Wang, Pengpeng Sang, Wei Wei, Yuan Li, Jiezhi Chen
Summary: Power dissipation is a challenge for continuous size scaling in CMOS technology. A solution proposed by researchers is the use of intrinsic cold-source field-effect transistors (CS-FETs) based on transition-metal dichalcogenides nanoribbons to lower power consumption and improve performance.
ACS APPLIED NANO MATERIALS
(2022)
Article
Physics, Multidisciplinary
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Summary: In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) is proposed to improve the ON current (I-ON) by increasing the line-tunneling area. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter shows great potential for future low power applications.
Article
Computer Science, Information Systems
Liang Chen, Huimin Wang, Qianqian Huang, Ru Huang
Summary: In this work, a novel steep-slope negative quantum capacitance field-effect transistor (NQCFET) with MoS2-integrated gate stack was realized. The optimized MoS2-integrated NQCFET demonstrated sub-60 mV/dec subthreshold swing over a current range of 5 decades, with the minimum SS reaching 29 mV/dec, indicating its remarkable potential for ultra-low power applications.
SCIENCE CHINA-INFORMATION SCIENCES
(2023)
Article
Engineering, Electrical & Electronic
Jae Seong Lee, Jisoo Yoon, Woo Young Choi
Summary: In this study, a nano-electromechanical-switch-based ternary content-addressable memory (NEMTCAM) is introduced for nearest neighbor (NN) classifier to overcome the bottleneck in conventional NN search architecture. NEMTCAM can perform parallel search operations to compute Hamming distance between input and stored vectors. Experimental demonstrations of NEMTCAM operation are provided, and an analytical model is presented to evaluate NN search accuracy, considering cell-to-cell parasitic resistance.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Jisoo Yoon, Hyug Su Kwon, Woo Young Choi
Summary: In this study, monolithic three-dimensional (M3D) multilayer nanoelectromechanical (NEM) memory switches were experimentally demonstrated for reconfigurable multi-path routing. The multi-layer NEM memory switch has moving mechanical beams in different metal layers, operating independently and nonvolatilely, including high impedance states. It is predicted that n-layer NEM memory switches utilizing n metal layers will exhibit 3((n-1)) x higher routing flexibility and nx higher chip density than conventional single-layer NEM memory switches.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Computer Science, Information Systems
Hyunju Kim, Mannhee Cho, Sanghyun Lee, Hyug Su Kwon, Woo Young Choi, Youngmin Kim
Summary: Content-addressable memory (CAM) conducts a parallel search operation by comparing search data with all content stored in memory in a single cycle, rather than using an address. This paper introduces a static-based architecture for low-power, high-speed BCAM and TCAM, utilizing NEM memory switch for nonvolatile data storage. The proposed CAM design shows significant improvements in propagation delay, matching power, and area compared to conventional designs.
Article
Engineering, Electrical & Electronic
Jin Ho Chang, Ji Ho Uhm, Hyug Su Kwon, Eunmee Kwon, Woo Young Choi
Summary: The influence of CHRR on HC VNAND flash memory was investigated and a recessed channel HC VNAND flash memory cell was proposed to address the issues.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Tae-Hyeon Kim, Kyungho Hong, Sungjoon Kim, Jinwoo Park, Sangwook Youn, Jong-Ho Lee, Byung-Gook Park, Hyungjin Kim, Woo Young Choi
Summary: In this study, a fuse device was developed for hardware neural network pruning. The device was characterized in a 1F1R structure and achieved a blow time of 0.4 µs and read endurance of >10^7. A fuse design method was also developed to adjust blow voltage and current, enabling the fuse to be used in various synaptic devices. Simulation results demonstrated the performance improvement achieved by disconnecting defective devices through fuse operations during network pruning.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Nanoscience & Nanotechnology
Suhyun Bang, Sungjoon Kim, Kyungho Hong, Kannan Udaya Mohanan, Seongjae Cho, Woo Young Choi
Summary: In this work, a memristor using Si nano-tip bottom electrode was fabricated and evaluated. The results showed significant improvements in area, current, and power consumption, making it a potential candidate for neuromorphic applications.
Article
Computer Science, Hardware & Architecture
Junmo Lee, Joon Hwang, Youngwoon Cho, Min-Kyu Park, Woo Young Choi, Sangbum Kim, Jong-Ho Lee
Summary: This article introduces a hardware-efficient on-chip weight update scheme called CRUS, which algorithmically mitigates the nonlinear weight update in synaptic devices. By introducing the update noise (UN) metric and adjusting the LTD skip conditions, CRUS achieves over 90% accuracy on the MNIST dataset and exhibits robustness to cycle-to-cycle variations.
IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS
(2022)
Article
Engineering, Electrical & Electronic
Ji Ho Uhm, Jin Ho Chang, Joonggyu Kim, Eunmee Kwon, Woo Young Choi
Summary: The reliability issues of the hemi-cylindrical (HC) vertical NAND (VNAND) flash memory were investigated with various channel hole remaining ratios (CHRRs). The nonuniform injection of carriers to the charge-trapping layer during program/erase operations in the case of HC VNAND was observed. A novel charge redistribution mechanism called azimuthal redistribution (AR) was proposed in addition to the conventional lateral migration. Simulation and experimental results showed that AR played a significant role in the data retention of HC VNAND cells as a function of the CHRR.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Taejin Jang, Bosung Jeon, Seunghwan Song, Woo Young Choi
Summary: A poly-Si overpass channel synaptic (OCS) transistor is proposed for low-power operation and low RC delay in neuromorphic systems. The OCS transistor has advantages in reducing on-current to sub 100 nA with high on/off ratio and finely dividing synaptic weights. Experimental demonstrations show the suitability of the OCS array for vector-matrix multiplication (VMM) operation and the adjustment of synaptic weights in sub-nA resolution. Classification accuracy of the fashion MNIST dataset remains high even after one year with four-bit quantization of spiking neural network (SNN).
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Jangsaeng Kim, Young-Tak Seo, Wonjun Shin, Woo Young Choi, Byung-Gook Park, Jong-Ho Lee
Summary: In this study, we propose an efficient exploration method using the low-frequency noise of synaptic devices, which is applicable to hardware-based deep Q-networks. The proposed method achieves exploration efficiently with a relatively low hardware burden compared to other published studies. A rounded dual-channel flash memory cell is utilized as the synaptic device. The performance evaluation based on a simple Snake game demonstrates that the proposed system achieves similar performance to that using the epsilon-greedy exploration method, even with a low noise level of the synaptic devices and without the need for an additional circuit.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Automation & Control Systems
Jae Seung Woo, Chae Lin Jung, Ki Ryung Nam, Woo Young Choi
Summary: This study experimentally demonstrates the potential of charge-trapping tunnel field effect transistors (CT-TFETs) for energy-efficient large-scale neuromorphic arrays. Compared to CT-MOSFET arrays, CT-TFET arrays exhibit higher accuracy, lower power consumption, and stronger immunity against voltage (IR) drops, making them suitable for large-scale neuromorphic applications.
ADVANCED INTELLIGENT SYSTEMS
(2023)
Article
Computer Science, Information Systems
Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, Woo Young Choi
Summary: The snapback breakdown behavior of multi-finger MOSFETs was studied using device simulation. It was found that the snapback breakdown voltage (SNBV) varies depending on the source/drain configuration, even with the same two-finger structure. This variation is attributed to hole current crowding beneath the shared source, which increases forward biasing at the source-substrate junction and prematurely activates the parasitic bipolar junction transistor (BJT). Double-pocket implantation successfully suppresses hole current crowding and achieves higher SNBV for two-finger MOSFETs.
Article
Computer Science, Information Systems
Ki Ryung Nam, Kwang Soo Kim, Woo Young Choi
Summary: The effects of low net-doped region on the electrical performance of tunnel field-effect transistors (TFETs) were investigated using a TCAD simulation. The low net-doped region between the source and pocket was found to enhance TFET electrical characteristics, such as the on-current (I-on) and subthreshold swing (SS), with a fine on-off current ratio (I-on/I-off). By optimizing the length of the low net-doped region, I-on increased 14.6 times and SS was reduced by 34.6% compared to TFETs without the low net-doped region. Guidelines for designing counter-doped pocket considering the low net-doped region were proposed.
Article
Computer Science, Information Systems
Jae Seung Woo, Jang Woo Lee, Woo Young Choi
Summary: The hot carrier injection (HCI) of tunnel field-effect transistors (TFETs) is quantitatively analyzed for the first time in terms of HCI-induced gate current, HCI probability, potential energy, and lateral/vertical electric field. The TFETs show higher HCI probability than MOSFETs under all bias conditions due to the strong peak lateral field at the source-channel junction. The optimal HCI bias condition of TFETs is also examined.
Article
Engineering, Electrical & Electronic
Jang Woo Lee, Jae Seung Woo, Woo Young Choi
Summary: This article demonstrates the experimental realization of a synaptic cell composed of two TFETs capable of performing XNOR operation in binary neural networks. The proposed synaptic TFETs exhibit lower current during inference and higher programming efficiency during weight transfer compared to conventional synaptic transistors. Additionally, the fabricated synaptic TFET arrays meet the energy requirement and have a low bit-error rate.
IEEE ELECTRON DEVICE LETTERS
(2022)
