Article
Chemistry, Analytical
Haiwu Xie, Hongxia Liu
Summary: This paper proposes a new type of heterostructure junctionless tunnel FET biosensor with an embedded nanogap, which can electrically sense the characteristics of biomolecules. The detection sensitivity of different biomolecules can be adjusted by two different gates. The influence of different gate work functions and dielectric constants on sensitivity is explored, and the simulation results show high switch ratio and sensitivity for the proposed biosensor.
Review
Chemistry, Physical
Manish Kumar Rai, Abhinav Gupta, Sanjeev Rai
Summary: The paper focuses on the bottleneck of leakage current in MOS devices with the growth of semiconductor industry. It investigates a detailed comparative analysis of various leakage currents with or without short channel effects, and explores techniques to minimize the leakage. Quantitative analysis of leakage affecting various short channel devices has been performed.
Article
Engineering, Electrical & Electronic
Jiale Sun, Yuming Zhang, Hongliang Lv, Zhijun Lyu, Bin Lu, Yi Zhu, Yuche Pan
Summary: In this paper, a ternary surface tunneling field effect transistor (TF-TFET) is designed and fabricated based on the tunneling mechanism. By adjusting the parameters and bias voltage, the transistor introduces a stable intermediate state between the switching states of conventional binary TFET devices, realizing the function of a ternary logic device. The device can convert between ternary logic and binary logic devices under certain conditions, and realize various functions. The compatibility of the fabrication process with the traditional CMOS process is of great significance for realizing the development of the ternary logic operation unit.
SOLID-STATE ELECTRONICS
(2023)
Article
Nanoscience & Nanotechnology
Wei Li, Qingrui Jia, Yumei Pan, Xi'an Chen, Yue Yin, Yupan Wu, Yucheng Wang, Yi Wen, Chao Wang, Shaoxi Wang
Summary: This study proposed a novel T-shaped gate TFET based on silicon with ferroelectric material, NC-TGTFET, which exhibits a steep subthreshold swing and high on-state current. Analysis using simulation tools explored the influences of thickness, doping concentration, and ferroelectric material properties on the characteristics of NC-TGTFET.
Article
Engineering, Electrical & Electronic
Km Sucheta Singh, Satyendra Kumar, Kaushal Nigam
Summary: This study investigates the applicability of DMGOSDG-TFET as a biosensing element and introduces new methods for implementing a biosensor based on DMGOSDG-TFET. The research shows that DMGOSDG-TFET has potential sensitivity and performance for biosensing applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Chemistry, Physical
M. D. Yasir Bashir, Mohd. Adil Raushan, Shameem Ahmad, Mohammed Jawaid Siddiqui
Summary: This study introduces a dual material gate with dual-k dielectric gate oxide double gate junctionless transistor, which shows suppressed leakage current in the off state and superior performance in various metrics such as transconductance, early voltage, and intrinsic gain. Additionally, further improvements are achieved by adding high-k gate sidewall spacers.
Article
Engineering, Electrical & Electronic
Mohammad K. Anvarifard, Ali A. Orouji
Summary: The study successfully adjusted the energy band of a novel Si0.7Ge0.3 source TFET, improving its performance for potential application in both analog and digital applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Physics, Multidisciplinary
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Summary: In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) is proposed to improve the ON current (I-ON) by increasing the line-tunneling area. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter shows great potential for future low power applications.
Article
Crystallography
Zhihua Zhu, Zhaonian Yang, Xiaomei Fan, Yingtao Zhang, Juin Jei Liou, Wenbing Fan
Summary: The tunnel field-effect transistor (TFET) is a potential candidate for ESD protection in a whole-chip, with the Ge-source TFET offering lower trigger voltage and higher failure current compared to traditional TFETs, but also showing vulnerability due to low thermal instability. By selecting the proper germanium mole fraction, the discharge ability and thermal failure risk can be balanced to enhance whole-chip ESD robustness.
Article
Engineering, Electrical & Electronic
K. Vanlalawmpuia, Aditya Sankar Medury
Summary: In this article, the impact of ferroelectric layer thickness (tFE) on the electrical parameters of a negative capacitance dual stacked-source tunnel field-effect transistor (NCDSS-TFET) is systematically investigated using TCAD simulator. Increasing tFE leads to higher ION/IOFF current ratio and better subthreshold swing (SS) with negligible hysteresis. However, it also introduces negative differential resistance (NDR) which is undesirable for analog circuit applications. The NCDSS-TFET device is further optimized to eliminate NDR effects by engineering the drain. The analog/RF performance of the drain-engineered NCDSS-TFET is investigated and found to be improved by increasing the drain underlap length, making it suitable for high-performance and ultralow power analog applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Chemistry, Physical
Bhaskar Kumar, Bharat Gupta, Sangeeta Singh, Pankaj Kumar
Summary: The study shows that the combination of FIN shaped gate with ground plane can alleviate the L-BTBT effect and improve the performance of JLFET. The proposed device demonstrates significant advantages, especially at sub-10 nm node, under the conditions of ultra-thin silicon thickness and high workfunction requirements.
Article
Chemistry, Physical
Satyendra Kumar, Km Sucheta Singh, Kaushal Nigam, Saurabh Chaturvedi
Summary: This research introduces a new dual-material double-source T-shaped tunnel field-effect transistor (TFET) to enhance tunneling efficiency and suppress ambipolar current conduction. By utilizing two sources and gate work function engineering, the device achieves a significant improvement in current and switching ratio. Simulation results demonstrate that the investigated TFET architecture successfully eliminates ambipolar current and exhibits better performance in terms of switching ratio.
Article
Engineering, Electrical & Electronic
Junfeng Hu, Yabin Sun, Ziyu Liu, Xiaojin Li, Yanling Shi
Summary: In this article, a novel structure of reconfigurable field-effect transistor (RFET) with arch-shaped control gate (ASG)-RFET is presented. The ASG-RFET exhibits significant improvement in ON-state current and propagation delay. Through TCAD simulations, the impact of geometry parameters on the transistor performance and the current enhancement mechanism are investigated. It is found that the tunneling rate and tunneling area are increased significantly in the novel RFET, and the combined action of ON-state current and gate capacitance leads to a significant decrease in propagation delay.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Sufen Wei, Guohe Zhang, Li Geng, Zhibiao Shao, Cheng-Fu Yang
Summary: This paper presents two novel silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), a lateral dual-gate TFET and a lateral triple-gate TFET, which demonstrate higher on-state current and lower off-state current due to the modulation effect of multiple gate voltages on the channel barrier. Comparison reveals that the lateral triple-gate TFET outperforms the dual-gate TFET in terms of on-state current and off-state current.
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS
(2021)
Article
Engineering, Electrical & Electronic
Neha Kamal, Alok Kumar Kamal, Jawar Singh
Summary: The article demonstrates an L-shaped tunnel field-effect transistor (LTFET)-based 1T DRAM with SiGe storage region, which improves sense margin (SM) and retention time (RT) compared to TFET-based 1T DRAMs. Simulation results show that the LTFET 1T DRAM exhibits good performance at different operating temperatures and gate lengths.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Chemistry, Physical
Satyendra Kumar, Kaushal Nigam, Saurabh Chaturvedi, Areeb Inshad Khan, Ashika Jain
Summary: This paper proposes the use of a low work function metal strip in a conventional double-gate TFET to enhance performance, resulting in the LWLS-DG-TFET structure. By implanting the metal strip, the tunneling rate is increased and on-current conduction is improved, leading to optimized TFET performance.
Article
Chemistry, Physical
Kaushal Nigam, P. N. Kondekar, Bandi Venkata Chandan, Satyendra Kumar, Vinay Anand Tikkiwal, Dharmender, Km. Sucheta Singh, Eshaan Bhardwaj, Shubham Choubey, Savitesh Chaturvedi
Summary: This study investigated a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) to overcome fabrication complexity and improve device performance. By introducing a dual layer oxide and live strip, the ON state current was enhanced, contributing to improved device gain and design of analog and RF circuits.
Article
Chemistry, Physical
Kaushal Nigam, Sajai Vir Singh, Priyanka Kwatra
Summary: This study investigated the reliability of stacked oxide heterogeneous gate dielectric polarity gate junction less tunnel FET, demonstrating a reduction in leakage current and improved channel interface quality. Compared to conventional polarity gate JLTFET, the SO PG JLTFET shows lower sensitivity to interface charges, showcasing potential for improved device performance.
Article
Chemistry, Physical
Prabhat Singh, Dharmendra Singh Yadav
Summary: In this paper, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized for enhanced analog/RF performance. Optimization of various parameters led to improved characteristics such as turn ON-voltage, sub-threshold swing, and I-on/I-off ratio. The reduction in parasitic capacitance also contributed to better RF performance and channel control.
Article
Chemistry, Physical
Sachin Kumar, Dharmendra Singh Yadav
Summary: This manuscript presents a detailed investigation on the impact of interface trap charges on the performance parameters of a proposed TFET device. The study shows that the proposed device exhibits improved current carrying capability and suppressed ambipolar behavior with a steeper subthreshold swing. It further demonstrates that the proposed TFET has negligible distortion in linearity parameters and is suitable for ultra-low power high-frequency electronic devices.
Article
Chemistry, Physical
Dharmendra Singh Yadav, Somya Saraswat
Summary: This manuscript aims to design an optimized TMG FinFET by applying dielectric material engineering, investigating the impact of temperature variation on device performance parameters and linearity parameters.
Article
Chemistry, Physical
Manshi Kamal, Dharmendra Singh Yadav
Summary: This study investigates the effects of temperature variation on HGO-DW-SCTFET, showing that the device performs better at different temperatures and can be used for high temperature applications.
Article
Chemistry, Physical
Prabhat Singh, Dharmendra Singh Yadav
Summary: Vertical TFET formations enable better control over the gate and inhibit direct source to drain tunneling through the entire gate region. The LTFET has a wider tunnel area compared to the standard TFET, leading to improved on-state current. However, it suffers from poor switching performance due to higher ambipolar current and low on/off ratio. This study focuses on enhancing the on/off ratio by introducing a drain underlap structure and high-k gate oxide, resulting in improved DC/RF and linearity performance.
Article
Chemistry, Physical
Dharmendra Singh Yadav, Manshi Kamal
Summary: This manuscript focuses on the effects of temperature and Interface trap charges on the proposed Hetero Gate Oxide-Dual Work function-Step Channel Tunnel Field Effect Transistor (HGO-DW-SC-TFET). It demonstrates that implementing hetero gate oxide with dual work-function improves crucial device performance parameters. The analysis includes examining the DC, Analog/Radio Frequency, and linearity figures of merit at various temperatures and ITCs. The results provide valuable insights for understanding and optimizing the performance of the HGO-DW-SC-TFET device.
Article
Computer Science, Hardware & Architecture
Mukesh Kumar Bind, Kaushal Nigam, Sajai Vir Singh
Summary: This paper proposes an electrically doped cavity on source junctionless tunnel field-effect transistor (ED-CS-JLTFET)-based biosensor for label-free detection of biomolecules. The proposed biosensor utilizes the electrically doped concept to reduce fabrication complexity and cost, and its sensing performance and sensitivity are evaluated through simulations.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
(2023)
Article
Chemistry, Physical
Priyanka Kwatra, Kaushal Nigam, Sajai Vir Singh
Summary: In this study, reliability analysis was conducted for the first time on Stacked Oxide Extended-Source Double-Gate Tunnel FET (SO-ESDG-TFET). It was found that SO-ESDG-TFET is less sensitive to interface trap charges compared to conventional ESDG-TFET, making it suitable for low-power applications.
Article
Engineering, Electrical & Electronic
Priyanka Kwatra, Sajai Vir Singh, Kaushal Nigam
Summary: This manuscript examines the device reliability of a lateral dual gate oxide bilateral tunnelling-based Tunnel FET (BT-TFET), which shows enhanced performance parameters compared to the conventional device. Positive and negative interface trap charges have different effects on the DC and Analogue/RF attributes of BT-TFETs and single gate oxide (SGO) BT-TFETs. The study also investigates linearity distortion parameters and transient analysis, finding that positive (negative) interface traps enhance (reduce) specific performance parameters of both BT-TFETs.
MICROELECTRONICS RELIABILITY
(2023)
Article
Computer Science, Hardware & Architecture
Kaushal Kumar Nigam, Dharmender, Vinay Anand Tikkiwal, Mukesh Kumar Bind
Summary: In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si-SiO2 interface. The impact of both positive and negative trap charges on various performance parameters has been studied, and the results have shown that DMSGO-SDP-TFET is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
(2023)
Article
Nanoscience & Nanotechnology
Dharmendra Singh Yadav, Prabhat Singh, Prajawal Roat
Summary: This research investigates the variations in source pocket length at the corner region of the source-channel interface with hetero-oxide triple metal gate. The study analyzes various DC and analog parameters including energy band profile, electric field, potential, transconductance, capacitance, cut-off frequency, gain bandwidth product, transit time, and linearity figure of merit. The findings show that the overall device performance of the TMG-HO-CSP-DGTFET is enhanced through the variation of source pocket length while keeping other factors constant.
Article
Computer Science, Information Systems
Indra Kumar Shah, Tanmoy Maity, Yogendra Singh Dohare, Devvrat Tyagi, Deepak Rathore, Dharmendra Singh Yadav
Summary: In this paper, a new energy minimization strategy for multi-hop wireless sensor network is proposed. It utilizes dynamic duty cycle allocation and optimum route selection to reduce energy consumption, and outperforms existing protocols in terms of performance.
