4.6 Article

A 32-Stage 15-b Digital Time-Delay Integration Linear CMOS Image Sensor With Data Prediction Switching Technique

期刊

IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 64, 期 3, 页码 1167-1173

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2017.2655143

关键词

CMOS image sensors (CISs); signal-to-noise ratio (SNR); time-delay integration (TDI)

资金

  1. Ministry of Science and Technology, Taiwan [MOST 104-2220-E-007-009, 104-2221-E-007-103-MY3]

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This paper presents a 512-column linear CMOS image sensor (CIS) with 32-stage digital time-delay integration (TDI) operation. A signal processing architecture consists of analog-front-ends, analog-to-digital converters (ADCs), and digital accumulators (DAs) are designed with optimization of timing, area, and power efficiency. An eight-column-shared 10-b successive approximation register ADC with data prediction switching technique and 11-b DA are proposed to achieve a data depth of 15 b after 32-stage TDI. The achieved signal-to-noise ratio boost is 14.84 dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11-mu m TSMC backside illumination CIS technology with a line time of 104 mu s, a pixel pitch of 7.5 mu m, and a power consumption of 153.2 mu W/column.

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