Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

标题
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design
作者
关键词
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出版物
出版商
Institute of Electrical and Electronics Engineers (IEEE)
发表日期
2017-08-05
DOI
10.1109/tcsi.2017.2728802

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