期刊
IEEE ELECTRON DEVICE LETTERS
卷 38, 期 4, 页码 509-512出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2017.2670925
关键词
Power transistors; vertical GaN FET; top-down; wet etch; bulk GaN substrate; e-mode; field plate
资金
- ARPA-E SWITCHES Program
- National Science Foundation [DMR-1419807]
This letter reports a GaN vertical fin power field-effect-transistor structure with submicron fin-shaped channels on bulk GaN substrates. In this vertical transistor design only n-GaN layers are needed, while no material regrowth or p-GaN layer is required. A combined dry/wet etch was used to get smooth fin vertical sidewalls. The fabricated transistor demonstrated a threshold voltage of 1 V and specific on resistance of 0.36m Omega cm(2). By proper electric field engineering, 800 V blocking voltage was achieved at a gate bias of 0 V.
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