N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

(2022) Shou-Yen Chao et al.   Crystals

Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

(2021) Yoongeun Seon et al.   Electronics

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

(2021) Khwang-Sun Lee et al.   Electronics

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

(2020) Junjie Li et al.   Nanomaterials

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

(2020) V. Jegadheesan et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

(2019) Yunho Choi et al.   SOLID-STATE ELECTRONICS

Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node

(2019) Jungmin Hong et al.   Micromachines

I-V model of nano nMOSFETs incorporating drift and diffusion current

(2018) Heng-Sheng Huang et al.   VACUUM

In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors

(2010) Wei-Chen Chen et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES