Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 mu m depth embedded in 0.18 mu m CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

Automated summary

This paper introduces a Cu-filled via-middle TSV embedded in 0.18 μm CMOS process for sensor application, focusing on the analysis and optimization of TSV leakage. By optimizing etch process, substrate defect, and thermal processing, TSV leakage failure can be effectively avoided, providing guidance for improving TSV wafer-level package yield and device performance in advanced semiconductor technology.