Article
Engineering, Electrical & Electronic
Yeong-Hun Park, Boram Yi, Seung-Hwan Kim, Ju-Hyun Shim, Hyeong-Sub Song, Hyun-Dong Song, Hyun-Jin Shin, Hi-Deok Lee, Ji-Woon Yang
Summary: In this paper, analytical models for low-frequency noise (LFN) characteristics of planar-type tunnel field-effect-transistors (TFETs) are proposed. A current-voltage model based on surface potential is developed to represent current fluctuations due to charge trapping/detrapping in the gate dielectric. The proposed model is validated using Technology Computer Aided Design (TCAD) and measurement data, showing good agreement. This analytical model not only serves as a valuable tool for low-power analog circuit design, but also offers physical insights into the LFN of TFETs.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Km Sucheta Singh, Satyendra Kumar, Kaushal Nigam
Summary: This study investigates the applicability of DMGOSDG-TFET as a biosensing element and introduces new methods for implementing a biosensor based on DMGOSDG-TFET. The research shows that DMGOSDG-TFET has potential sensitivity and performance for biosensing applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Abhinav Gupta, Sneh Saurabh
Summary: This article proposes a standard ternary inverter based on a dual-pocket tunnel FET for low-power applications, demonstrating that appropriate doping concentration and length choices can result in three stable output voltage levels. The ternary inverter characteristics are achieved through two tunneling mechanisms in the device, allowing for operation at different supply voltages by controlling the pocket doping concentration.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Namrata Shaw, Bratati Mukhopadhyay
Summary: This article introduces a split-gate T-shape channel DM DGTFET with a DP for the first time, which can be used as a label-free biosensor. The analytical model and validation of the device are presented. The performance of the proposed TFET in terms of threshold voltage, subthreshold slope, ON current, and OFF current is thoroughly investigated.
IEEE SENSORS JOURNAL
(2023)
Article
Engineering, Electrical & Electronic
Mohammad K. Anvarifard, Ali A. Orouji
Summary: The study successfully adjusted the energy band of a novel Si0.7Ge0.3 source TFET, improving its performance for potential application in both analog and digital applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Physics, Condensed Matter
Garima Jain, Ravinder Singh Sawhney, Ravinder Kumar, Girish Wadhwa
Summary: An analytical model of dual material single gate doping-less Tunnel FET (DM-GU-TFET) with gate underlap regions has been proposed and validated using TCAD simulation. The study examines the potential of gate underlap area with channel area and proposes an explanatory estimate strategy to settle the Poisson equations at different limit conditions. It is found that structural variations such as gate underlap length and tunneling length have an impact on the electrical characteristics of DM-GU-TFET.
SUPERLATTICES AND MICROSTRUCTURES
(2021)
Article
Engineering, Electrical & Electronic
K. Vanlalawmpuia, Aditya Sankar Medury
Summary: In this article, the impact of ferroelectric layer thickness (tFE) on the electrical parameters of a negative capacitance dual stacked-source tunnel field-effect transistor (NCDSS-TFET) is systematically investigated using TCAD simulator. Increasing tFE leads to higher ION/IOFF current ratio and better subthreshold swing (SS) with negligible hysteresis. However, it also introduces negative differential resistance (NDR) which is undesirable for analog circuit applications. The NCDSS-TFET device is further optimized to eliminate NDR effects by engineering the drain. The analog/RF performance of the drain-engineered NCDSS-TFET is investigated and found to be improved by increasing the drain underlap length, making it suitable for high-performance and ultralow power analog applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Physics, Multidisciplinary
Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
Summary: In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) is proposed to improve the ON current (I-ON) by increasing the line-tunneling area. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter shows great potential for future low power applications.
Article
Nanoscience & Nanotechnology
Wei Li, Qingrui Jia, Yumei Pan, Xi'an Chen, Yue Yin, Yupan Wu, Yucheng Wang, Yi Wen, Chao Wang, Shaoxi Wang
Summary: This study proposed a novel T-shaped gate TFET based on silicon with ferroelectric material, NC-TGTFET, which exhibits a steep subthreshold swing and high on-state current. Analysis using simulation tools explored the influences of thickness, doping concentration, and ferroelectric material properties on the characteristics of NC-TGTFET.
Article
Engineering, Electrical & Electronic
Karabi Baruah, Srimanta Baishya
Summary: A comprehensive study on the dielectrically modulated Ge-source short double-gate PNPN tunnel field-effect transistor (SG-PNPN TFET) based label-free biosensor is conducted. The short gates and counter-doped pockets in the SG-PNPN TFET architecture enhance band-to-band tunneling, thereby increasing the device's drain current sensitivity. By creating a nanocavity between the gate and SiO2 layer on the source side, the sensor's performance is evaluated in terms of dielectric constant and charge density of biomolecules. The proposed SG-PNPN TFET biosensor exhibits superior sensitivity compared to other FET-based biosensors, making it suitable for low-power biosensing.
MICROELECTRONICS JOURNAL
(2023)
Review
Chemistry, Physical
P. Hannah Blessy, A. Shenbagavalli, T. S. Arun Samuel
Summary: This study discusses the advantages of the 3 nm TFET structure in low-power applications and the importance of overcoming the limitations of CMOS transistors.
Article
Computer Science, Interdisciplinary Applications
Sabitabrata Bhattacharya, Suman Lata Tripathi, Vikram Kumar Kamboj
Summary: An improved version of Chimps optimizer algorithm, named Imp-Chimp, is proposed in this paper and is applied to optimize the performance of tunnel FET architectures for low power VLSI circuits. The proposed technique is validated on standard benchmarks and multidisciplinary engineering design problems, showing better performance compared to existing optimization methods. The paper also highlights the potential of tunnel field effect transistor (TFET) as a promising device for low power electronic circuits.
ENGINEERING WITH COMPUTERS
(2023)
Article
Engineering, Electrical & Electronic
Hyun Woo Kim, Daewoong Kwon
Summary: The L-shaped tunnel FET introduced in this work, engineered with pocket doping, demonstrates improved performance by suppressing corner tunneling and enhancing on/off transition. Through optimized pocket doping concentration, the subthreshold swing is reduced and the on-current is significantly increased compared to conventional L-shaped TFETs, even in devices with extremely scaled gate length.
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
(2021)
Article
Engineering, Electrical & Electronic
Sufen Wei, Guohe Zhang, Li Geng, Zhibiao Shao, Cheng-Fu Yang
Summary: This paper presents two novel silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), a lateral dual-gate TFET and a lateral triple-gate TFET, which demonstrate higher on-state current and lower off-state current due to the modulation effect of multiple gate voltages on the channel barrier. Comparison reveals that the lateral triple-gate TFET outperforms the dual-gate TFET in terms of on-state current and off-state current.
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS
(2021)
Article
Engineering, Electrical & Electronic
Alireza Aghanejad Ahmadchally, Morteza Gholipour
Summary: In this simulation-based study, an n-type six-dimer-line armchair graphene nanoribbon (6-AGNR) tunnel field-effect transistor with asymmetric reservoir doping density was investigated. The results show that for the device with a 5-nm channel length and a supply voltage of 0.4 V, it exhibited a high I-ON/I-OFF ratio and a low subthreshold swing.
JOURNAL OF COMPUTATIONAL ELECTRONICS
(2021)
Article
Engineering, Electrical & Electronic
Julia C. S. Sousa, Welder F. Perina, Roberto Rangel, Eddy Simoen, Anabela Veloso, Joao A. Martino, Paula G. D. Agopian
Summary: In this study, a Gate-All-Around Nanosheet transistor (GAA-NSH) was used to design an operational transconductance amplifier (OTA) operating from room temperature to 200 degrees C. The GAA-NSH design showed improved performance compared to FinFET and Tunnel FET (TFET) designs in terms of voltage gain, power consumption, and area footprint.
SOLID-STATE ELECTRONICS
(2022)
Article
Engineering, Electrical & Electronic
B. Cretu, A. Veloso, E. Simoen
Summary: DC and low frequency noise measurements were conducted on p-channel gate all around (GAA) vertically stacked silicon nanosheets (NS) at room temperature. The study estimated key DC parameters such as threshold voltage, low field mobility, access resistance, and subthreshold swing. Preliminary low-frequency noise studies suggested that the 1/f noise can be explained by carrier number fluctuation mechanism in weak to moderate inversion, while the access resistance noise prevails in strong inversion.
SOLID-STATE ELECTRONICS
(2022)
Article
Engineering, Electrical & Electronic
Bogdan Cretu, Anabela Veloso, Eddy Simoen
Summary: In this study, two types of GAA vertically stacked silicon nanosheet FETs were investigated, and principal electrical parameters were estimated using a refined Y-function methodology. The study found correlations between noise level and low field mobility.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
B. Cretu, A. Veloso, E. Simoen
Summary: This work investigates the DC and low frequency noise performance of p-channel gate-all-around (GAA) vertically stacked silicon nanosheets (NS) at room temperature. Methodologies that are not affected by access resistance are used to estimate key DC parameters. Low frequency noise studies reveal that carrier number fluctuations correlated to mobility fluctuations explain the 1/f behavior in weak to moderate inversion. The impact of access resistance on Coulomb scattering coefficient estimation is also discussed, with access resistance noise dominating the total 1/f noise in strong inversion.
SOLID-STATE ELECTRONICS
(2023)
Article
Engineering, Electrical & Electronic
Bruno Godoy Canales, Welder Fernandes Perina, Joao Antonio Martino, Eddy Simoen, Uthayasankaran Peralagu, Nadine Collaert, Paula Ghedini Der Agopian
Summary: This paper investigates the characteristics of the MISHEMT device, focusing on the impact of multiple conductions on the intrinsic voltage gain. The study reveals that the total drain current of the device consists of three different components, leading to double drain voltage saturation and a double plateau in the output characteristics' saturation region. This behavior is influenced by the gate voltage, and therefore, the extraction of the output characteristics and analog parameters is bias-dependent. Furthermore, it is found that the intrinsic voltage gain increases in the second plateau where HEMT conduction dominates.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
(2023)
Article
Engineering, Electrical & Electronic
Rodrigo do Nascimento Toledo, Joao Antonio Martino, Paula Ghedini Der Agopian
Summary: This work presents hybrid low-dropout voltage regulators (LDO) designed with tunnel field-effect transistor (TFET) - metal-oxide semiconductor field-effect transistor (MOSFET) nanowire (NW) technologies. The devices were modeled using Verilog-A with lookup tables based on experimental data. The hybrid regulators combine NW-MOSFETs for high load current delivery and NW-TFETs for high gain and low power consumption. Two hybrid LDOs with different onset voltages were proposed. The Hybrid-ΔV LDO exhibited the best loop gain and low quiescent current, while the Hybrid-LS LDO showed good gain-bandwidth product. The use of TFET-MOSFET NW technologies enables LDOs with ultra-low power consumption and high loop gain.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
(2023)
Article
Engineering, Electrical & Electronic
V. C. P. Silva, J. A. Martino, E. Simoen, A. Veloso, P. G. D. Agopian
Summary: This study experimentally evaluates the performance of n-type gate-all-around vertically stacked nanosheet field effect transistors (NSFETs) with different gate lengths at various temperatures, focusing on their use in analog applications. The results show that the shorter transistors have better performance in analog applications. Additionally, as the temperature decreases, the carrier mobility and subthreshold swing of the transistors improve.
SOLID-STATE ELECTRONICS
(2023)
Proceedings Paper
Engineering, Electrical & Electronic
Welder F. Perina, Joao A. Martino, Paula G. D. Agopian
Summary: This work experimentally evaluates the multiple conductions of a GaN based MISHEMT in a temperature range from 200K to 450K, observing the changes in threshold voltage, subthreshold swing, and transconductance at different temperatures.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Arllen D. R. Ribeiro, Gustavo V. Araujo, Joao A. Martino, Paula G. D. Agopian
Summary: This paper analyzes the influence of uniaxially strained silicon on two-stage operational transconductance amplifiers designed with SOI FinFETs. The strain design improves the circuit performance by enhancing mobility, resulting in higher voltage gain and gain-bandwidth product.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Wenita De Lima Silva, Paula Ghedini Der Agopian, Joao Antonio Martino
Summary: This study presents the design of a Low Dropout Voltage Regulator (LDO) using Line-Tunnel Field Effect Transistor (Line-TFET), with the transistor modeled using Verilog-A and Lookup Table (LUT) obtained from experimental data. Despite having a lower Gain-BandWidth Product (GBW), the Line-TFET LDO delivers better results and higher efficiency compared to a MOSFET LDO, and can be designed without the need for compensation capacitor to achieve stability.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Rodrigo Do Nascimento Toledo, Joao Antonio Martino, Paula Ghedini Der Agopian
Summary: This work analyzes the application of vertical nanowire tunnel field-effect transistors (TFETs) and vertical nanowire MOSFET in low-dropout voltage regulator (LDO) design. Three TFETs with different sources are examined. The results show that TFET-based LDOs are stable and have good frequency response without the need for compensator capacitors. However, the MOSFET LDO has lower efficiency and requires additional capacitors for stability.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Raphael Gil Camargo, Joao Antonio Martino, Paula Ghedini Der Agopian
Summary: This paper presents the temperature influence on OTA designed with triple gate TFET and verifies the impact of using a current mirror bias circuit with or without thermal compensation. The results suggest that TFET transistors have lower power consumption and higher voltage gain compared to conventional MOS transistors in this kind of circuit. Additionally, it is observed that using a current bias circuit with temperature compensation can slightly increase the total gain of the circuit.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Henrique L. Carvalho, Ricardo C. Rangel, Katia R. A. Sasaki, Paula G. D. Agopian, Leonardo S. Yojo, Joao A. Martino
Summary: This work presents the experimental and simulated characteristics of a reconfigurable (SOI)-S-BE MOSFET transistor with non-sintered aluminum contact for the first time. The transistor has a higher current for electrons without the sintering process, but doesn't have significant current for holes. This finding can be utilized to improve future implementations of the (SOI)-S-BE MOSFET.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Lucas Almir Dos Santos Fernandes, Marco Isaias Alayo, Joao Antonio Martino
Summary: A Monte Carlo analysis was conducted to investigate the influence of device fabrication mismatch on the fractal zone of a fractal tree structure in fractional-order MOS Capacitors. The results indicated that there was a reasonable deviation of 18% and -14% for a tolerance of 20% in the devices values, and for 2 sigma above and below the median values of the width and initial frequency value of the fractal zone, respectively, which accounted for over 90% of the samples.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Pedro H. Duarte, Ricardo C. Rangel, Daniel A. Ramos, Leonardo S. Yojo, Carlos A. B. Mori, Katia R. A. Sasaki, Paula G. D. Agopian, Joao A. Martino
Summary: This study presents the fabrication and electrical characterization of the Ion-Sensitive Field Effect Transistor (ISFET) exposed to hydrogen peroxide solutions. Two configurations were set up to evaluate the sensitivity of the devices to the concentration of the solution. The results show that using two electrodes in the sample solution provides a higher sensitivity compared to measurements with one electrode.
2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022)
(2022)
