期刊
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
卷 69, 期 1, 页码 1114-1126出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2020.3039794
关键词
Receivers; Gain; Radio frequency; Phased arrays; Electronics packaging; Couplers; Array signal processing; Beam-to-beam isolation; current-sharing active combiner; multibeam phased-array receiver; RF~beamforming; variable-gain phase shifter (VG-PS)
资金
- National Natural Science Foundation of China [61731019, 61674128]
This article presents a four-element 7.5-9-GHz phased-array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. It features a low-power and compact design, achieving high performance with gm-based variable-gain phase shifter and current-sharing active combiner.
This article presents a four-element 7.5-9-GHz phased-array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes all the input elements to maximize the beamforming gain. To realize a low-power and compact design, the multielement multibeam phased-array architecture features the gm-based variable-gain phase shifter (VG-PS) and the current-sharing active combiner. The VG-PS with 6-bit phase resolution achieves <2 degrees root mean square (rms) phase error and <0.3 dB rms gain error at the maximum gain setting. The receiver demonstrates a 20-dB power gain, a 3.6-dB noise figure (NF), and a -19-dBm input 1-dB gain compression point (IP1dB) at 7.5-9 GHz for each element. The chip occupies 5.42 x 3.62 mm2 area excluding pads and consumes 860 mW, equivalent to the record low 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.
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