Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si CMOS Logic Circuit Performance in N-14 to N-7 Scaled Technologies

We have studied the impact of thermal contact resistance (TCR) (R-th) and within-chip ambient temperature (T-A) on the device self-heating effect (SHE) and its effect on transient and steady-state performance of Si 3-Fin FinFET-basedCMOS inverter (from N-14 to N-7 technologies) using coupled hydrodynamic-thermodynamic(HD-TH) mixed-mode simulations. The effect of the load capacitance (C-L) on device lattice temperature (T-L) and its impact on propagation delay (t(pd)) of the targetedCMOS inverter circuit are analyzed. The impact of technology scaling on SHE of inverter and its effect on circuit performance is also studied. We investigated the SHE in the 3-Fin FinFET-based ring oscillator (RO) and estimated the stage delay and frequency of oscillations. Our simulation results revealed that within-chip T-A and R-th of gate, source, and drain (R-th, G(SD)) have significant effect on the logic circuit performance in terms of degradation of noise margin (NM), inverter gain (vertical bar g(max)vertical bar), and increase in tpd due to SHE from N-14 to N-7 technologies.