期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 66, 期 9, 页码 3571-3584出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2019.2925826
关键词
Sparse code multiple access (SCMA); low-density parity-check (LDPC); iterative detection-and-decoding (IDD); fifth-generation (5G) communication; CMOS digital integrated circuits
资金
- Ministry of Science and Technology, Taiwan [MOST 104-2220-E-002-017, MOST 106-2221-E-007-018-MY3]
- Center for Electronics Technology Integration from the Featured Areas Research Center Program within Ministry of Education (MOE) in Taiwan
This paper presents the first low-complexity realization of an LDPC-code sparse code multiple access (SCMA) receiver with a high-throughput LDPC decoder and a multi-mode SCMA detector. The minimum mean-square error with parallel interference cancellation (MMSE-PIC) algorithm is adopted in the SCMA detection. The modified user-node operations in the MMSE-PIC-based message-passing detector improve the convergence rate in error performance. The proposed receiver also supports multi-user iterative detection and decoding (MU-IDD) to improve the error rate performance. The proposed receiver supports both 4x6 and 8x12 SCMA systems. The proposed MU LDPC decoder has a 57.1% lower hardware complexity than the direct-mapped design that is achieved through hardware sharing and memory access scheduling. Designed in a 40-nm CMOS technology, the SCMA receiver integrates 10.9M logic gates in an area of 3.382 x 3.382 mm(2). The proposed design achieves a gross throughput of 1.198 Gb/s and 599 Mb/s for 8 x 12 and 4 x 6 SCMA systems, respectively, under a practical situation. It dissipates 813 mW at a clock frequency of 300 MHz from a 0.9-V supply.
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