A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell

(2018) Ganapathi Hegde et al.   AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

Implementation of the DWT in a GPU through a Register-based Strategy

(2015) Pablo Enfedaque et al.   IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS

Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform

(2015) Anand Darji et al.   IET Computers and Digital Techniques

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT

(2012) Basant Kumar Mohanty et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

(2011) Basant K. Mohanty et al.   IEEE TRANSACTIONS ON SIGNAL PROCESSING

Efficient Multi-Input/Multi-Output VLSI Architecture for Two-Dimensional Lifting-Based Discrete Wavelet Transform

(2010) Xin Tian et al.   IEEE TRANSACTIONS ON COMPUTERS

An Efficient Architecture for 3-D Discrete Wavelet Transform

(2009) A. Das et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY

A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

(2009) Yeong-Kang Lai et al.   IEEE TRANSACTIONS ON CONSUMER ELECTRONICS