High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications

(2017) Shihao Wang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY

Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder

(2016) Chun-Yu Lung et al.   Journal of Real-Time Image Processing

A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding

(2015) Claudio M. Diniz et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Reconfigurable Interpolation Architecture for Multistandard Video Decoding

(2015) Gwo Giun Lee et al.   Journal of Signal Processing Systems for Signal Image and Video Technology

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

(2015) Grzegorz Pastuszak et al.   Journal of Signal Processing Systems for Signal Image and Video Technology

Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder

(2015) Grzegorz Pastuszak et al.   Journal of Real-Time Image Processing

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

(2014) Grzegorz Pastuszak et al.   Journal of Real-Time Image Processing

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder

(2010) Xianmin CHEN et al.   IEICE TRANSACTIONS ON ELECTRONICS

Subpixel Interpolation Architecture for Multistandard Video Motion Estimation

(2009) Liang Lu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY

A novel VLSI architecture of motion compensation for multiple standards

(2008) Junhao Zheng et al.   IEEE TRANSACTIONS ON CONSUMER ELECTRONICS