4.4 Article

Optimized photolithographic fabrication process for carbon nanotube devices

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AIP ADVANCES
卷 1, 期 2, 页码 -

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AIP Publishing
DOI: 10.1063/1.3582820

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资金

  1. JSTO DTRA
  2. Army Research Office [W911NF-06-1-0462]
  3. NSF [DMR-0805136]
  4. NCMR
  5. NSF/DIA [IIS-07-15024]
  6. Direct For Mathematical & Physical Scien
  7. Division Of Materials Research [0805136] Funding Source: National Science Foundation

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We have developed a photolithographic process for the fabrication of large arrays of single walled carbon nanotube transistors with high quality electronic properties that rival those of transistors fabricated by electron beam lithography. A buffer layer is used to prevent direct contact between the nanotube and the novolac-based photoresist, and a cleaning bake at 300C effectively removes residues that bind to the nanotube sidewall during processing. In situ electrical measurement of a nanotube transistor during a temperature ramp reveals sharp decreases in the ON-state resistance that we associate with the vaporization of components of the photoresist. Data from nearly 2000 measured nanotube transistors show an average ON-state resistance of 250 +/- 100 k Omega. This new process represents significant progress towards the goal of high-yield production of large arrays of nanotube transistors for applications including chemical sensors and transducers, as well as integrated circuit components. Copyright 2011 Author(s). This article is distributed under a Creative Commons Attribution 3.0 Unported License. [doi:10.1063/1.3582820]

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