Article
Engineering, Electrical & Electronic
Yidi Yin, Kean Boon Lee
Summary: This research presents an enhancement-mode p-channel GaN heterojunction field effect transistor with a metal-insulator-semiconductor gate structure, achieving excellent performance through various treatments.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Chemistry, Analytical
Shou-Yen Chao, Wen-How Lan, Shou-Kong Fan, Zi-Wen Zhon, Mu-Chun Wang
Summary: The decoupled-plasma nitridation treatment process is effective in repairing trap issues during high-k gate dielectric deposition. It not only improves electrical performance and reduces gate leakage, but also has an effect on channel length.
Article
Materials Science, Multidisciplinary
Seong-Hyun Hwang, Seung-Hwan Kim, Seung-Geun Kim, Min-Su Kim, Kyu-Hyun Han, Sungjoo Song, Jong-Hyun Kim, Euyjin Park, Dong-Gyu Jin, Hyun-Yong Yu
Summary: Two-dimensional atomic threshold switching field-effect transistors (ATS-FETs), combining 2D FET with threshold switching (TS) devices, improve subthreshold swing (SS) for low-power devices. This study investigates V-th engineering for industrial application of 2D ATS-FET by altering the counter electrode (CE) of a TS device.
MATERIALS TODAY ADVANCES
(2023)
Article
Engineering, Electrical & Electronic
Girish Pahwa, Pragya Kushwaha, Avirup Dasgupta, Sayeef Salahuddin, Chenming Hu
Summary: The study presents compact models that capture the effects of silicon carrier mobility and velocity saturation at low temperatures, as well as corrects the characteristics of FDSOI and Fin-FET devices at low temperatures within the industry-standard BSIM framework. New temperature-dependent mobility and velocity saturation models are proposed to accurately model behavior down to cryogenic temperatures, with observed dependencies attributed to higher rates of Coulomb scattering.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Computer Science, Information Systems
Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh
Summary: This paper presents a detailed study on the effect of drain induced barrier enhancement (DIBE) on the subthreshold swing and OFF-state current of a short channel MOSFET using calibrated 2-D simulations. The study demonstrates that gate-on-drain overlap in a short channel MOSFET leads to DIBE, resulting in near ideal subthreshold swing, reduced DIBL, constant threshold voltage, and improved ION/IOFF ratio at room temperature.
Article
Chemistry, Physical
Hossein Mohammadi, Mohammad Mohammadi, Iraj Sadegh Amiri, Mahdiar Hosseinghadiry
Summary: In this paper, a new structure of triple work function metal gate SOI MESFET device is proposed to alleviate the impact of drain potential and reduce DIBL effects. An analytical subthreshold model based on the exact solution of the Poisson equation in the channel region is developed and compared with conventional devices. The feasibility of device fabrication is demonstrated by using the TCAD simulator ATLAS from Silvaco.
Article
Engineering, Electrical & Electronic
Yan Liu, Lili Lang, Yongwei Chang, Yi Shan, Xiaojie Chen, Yemin Dong
Summary: The cryogenic performance of nanoscale CMOS transistors with a standard 55-nm Si-bulk technology was investigated through DC measurements. At lower temperatures, an increase in channel length significantly enhanced the cryogenic drain saturation current gain, while the response to width change was relatively weak. Additionally, the degraded sub-threshold swing due to the short channel effect was alleviated at lower temperatures.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Yu-Hsuan Chen, Hung-Jin Teng, Chen-Hsin Lien, Chun-Hsing Shih
Summary: This study numerically examined a Si-based asymmetric junctionless TFET (AJ-TFET) architecture for suppressing coupled short-channel and short-drain effects in and improving the on-current switching of TFET devices for ultralow-voltage CMOS applications. The results revealed that the AJ-TFET exhibited considerably lower swing levels and higher current levels compared to conventional PIN-TFETs, offering promising candidates for use in ultralow-voltage energy-efficient applications.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
(2022)
Article
Chemistry, Physical
Sweta Chander, Sanjeet Kumar Sinha
Summary: This paper presents a numerically simulated Ge-source based TFET with SiO2 segregation, which shows improved performance compared to conventional TFET. The device exhibits superior ON-state current and subthreshold swing, and has been studied in various aspects such as electrical characteristics and temperature variation. The proposed device offers high ON current, I-ON/I-OFF ratio, and enhanced SS, which have been validated through Silvaco Atlas TCAD.
Article
Chemistry, Multidisciplinary
Seung-Geun Kim, Seung-Hwan Kim, Gwang-Sik Kim, Hyeok Jeon, Taehyun Kim, Hyun-Yong Yu
Summary: A gate-connected MoS2 atomic threshold switching FET using a nitrogen-doped HfO2-based threshold switching device has been developed, achieving extremely low subthreshold swings and a high on-off ratio, with excellent optical properties for functioning as an infrared detectable phototransistor.
Article
Chemistry, Multidisciplinary
Juan Lyu, Jian Gong
Summary: It has been discovered that a two-dimensional semiconductor-semiconductor combination can also be used as an efficient cold source, as verified by computer simulation. By interfacing with n-doped HfS2, MoTe2 can be p-type-doped, reducing the subthreshold swing and enhancing the on-state current. A hybrid transport mechanism involving cold injection and tunneling effect is found in this p- and n-type HfS2/MoTe2 FET.
Article
Chemistry, Physical
Yograj Singh Duksh, Balraj Singh, Deepti Gola, Pramod Kumar Tiwari, Satyabrata Jit
Summary: This paper presents 2-D analytical models for GC-DG JLFETs, solving the 2-D Poisson's equation to determine the channel central potential and calculating threshold voltage, subthreshold current, and subthreshold swing. The validity of the model results is confirmed using TCAD numerical data obtained from a 2-D ATLAS device simulator from Silvaco.
Article
Engineering, Electrical & Electronic
Sukanta Kumar Swain, Sangita Kumari Swain, Shashi Kant Sharma
Summary: This study presents the simulation results of Mg2Si heterojunction-based SOI TFETs using TCAD. Mg2Si is utilized as the low-bandgap material for the source to achieve high on-current. The proposed structure enhances tunneling rate, leading to improved current conduction and subthreshold swing. The device exhibits on-current (I-ON), off-current (I-OFF), and subthreshold swing values of 1.089 x 10(-5)A/mu m, 8.632 x 10(-17)A/mu m, 1.26 x 10(11), and 27 mV/decade, respectively. Additionally, a systematic study on the physical interpretation of electron Fermi potential, DC, and analog/RF performance has been conducted. The proposed device follows the ITRS roadmap for low power switching performance.
JOURNAL OF COMPUTATIONAL ELECTRONICS
(2023)
Article
Physics, Condensed Matter
Te-Kuang Chiang
Summary: A model for short-channel subthreshold current in elliptical nanowire FETs caused by interface-trapped charge was established using quasi-3D potential approach and drift-diffusion model. The positive and negative interface-trapped charges were found to degrade the high and low output voltages of N-FET/P-FET, respectively. Short-channel effects on subthreshold current and logic swing can be controlled by selecting the scaling factor, with the minimum factor uniquely determining the minimum LS degradation for the subthreshold logic gate.
SUPERLATTICES AND MICROSTRUCTURES
(2021)
Article
Chemistry, Multidisciplinary
Hsin-Chia Yang, Sung-Ching Chi, Wen-Shiang Liao
Summary: In the deep submicron regime, FinFET effectively suppresses leakage current using a 3D fin-like channel substrate. However, the subsequent anisotropic plasma dry etching process presents challenges due to dimension loss. Measurement and analysis of the prepared transistors provide important conclusions and potential applications.
APPLIED SCIENCES-BASEL
(2022)
Article
Engineering, Electrical & Electronic
Deepak Kumar Jarwal, Ashwini Kumar Mishra, Kamalaksha Baral, Amit Kumar, Chandan Kumar, Gopal Rawat, Bratindranath Mukherjee, Satyabrata Jit
Summary: This article discusses the direct effect of the seed layers on the growth of ZnO nanorods and the photovoltaic parameters of hybrid perovskite solar cells. Different types of ZnO seed layers were prepared and analyzed, and it was found that the seed layer based on ZnO quantum dots showed the best alignment, vertical arrangement, and uniform distribution of ZnO nanorods, leading to improved performance of the solar cells.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Chemistry, Physical
Hemlata Bisht, Abhinav Pratap Singh, Hem Chandra Joshi, Satyabrata Jit, Hirdyesh Mishra
Summary: In this study, the electronic excitation energy transfer between two p-type fluorescent semiconductors, F8BT and TIPS-P, was investigated in a chloroform solution using fluorescence techniques. It was found that the deviation from the Förster theory at lower acceptor concentrations is a result of diffusion and energy migration, while the system follows the Förster model of resonance excitation energy transfer at higher acceptor concentrations. The appearance of rise time and its decrease with acceptor concentration confirms FRET from F8BT to TIPS-P.
JOURNAL OF PHYSICAL CHEMISTRY B
(2022)
Article
Chemistry, Physical
Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, Satyabrata Jit
Summary: In this work, a gate stacked hetero-junction TFET on SELBOX substrate (GSHJ-STFET) is proposed and compared with fully depleted SOITFET in terms of electrical performance. The optimized TFET structure shows better static performance compared to conventional fully depleted SOI-TFET. Furthermore, the temperature reliability of both structures is extensively investigated.
Article
Engineering, Electrical & Electronic
Ajay Kumar Dwivedi, Saumya Tripathi, Rishi Tripathi, Satyabrata Jit, Shweta Tripathi
Summary: This study proposes a flexible organic-inorganic heterojunction-based UV photodetector, fabricated using a low-cost spin coating method. The proposed structure exhibits excellent performance parameters and shows remarkable performance in the UV region.
IEEE PHOTONICS TECHNOLOGY LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Azam Malekpoor, Seyed Amir Hashemi, Satyabrata Jit
Summary: A quantum phase slip junction-based direct inverter gate is proposed for the first time, which has a simpler structure and smaller size compared to the indirectly designed inverter.
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
(2022)
Article
Engineering, Electrical & Electronic
Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, Satyabrata Jit
Summary: This article presents a dielectric-modulated ultrasensitive label-free biosensor based on GaSb/GaAs type-II heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed sensor utilizes the SELBOX substrate to enhance its performance and reduce lattice heat. The dual-cavity (DC) HJ-STFET structure with cavities in the gate oxide is used to detect biomolecules through gate-dielectric modulation.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Engineering, Electrical & Electronic
Ajay Kumar Dwivedi, Rishi Tripathi, Saumya Tripathi, Satyabrata Jit, Shweta Tripathi
Summary: This letter proposes a SnS2/PEDOT:PSS based heterojunction UV-visible light photodetector which shows high responsivity, external quantum efficiency, detectivity, and sensitivity. The device also exhibits fast response time and fall time.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Materials Science, Multidisciplinary
Rishibrind Kumar Upadhyay, Satyabrata Jit
Summary: This paper presents an inverted structure UV-visible-Near Infrared (NIR) broadband photodetector featuring ZnO Nanoparticles (NPs)/CH3NH3PbI3/PTB7/MoO3/Ag. The ZnO NPs layer serves as the electron transport layer (ETL), CH3NH3PbI3 functions as the active layer, PTB7 acts as the hole transport layer (HTL), and MoO3 is utilized to optimize the recombination current in the photodetector structure. The proposed device exhibits desirable optical and electrical characteristics, with a maximum photoresponsivity of -0.36 A/W, detectivity of -7.8x1012 Jones, and external quantum efficiency (EQE) of -83.67% under a bias voltage of -2 V. The rise time and fall time are measured as 81 ms and 75 ms, respectively.
Article
Engineering, Electrical & Electronic
Ajay Kumar Dwivedi, Satyabrata Jit Sr, Shweta Tripathi Sr
Summary: In this study, a semiconductor-insulator-semiconductor (SIS) structure based ultraviolet-visible light photodetector is proposed. Tungsten diselenide (WSe2) and tin disulfide (SnS2) are used as semiconductors, and aluminium oxide (Al2O3) is used as an insulator in the structure. The photodetector is fabricated on a flexible ITO coated PET substrate using a low-cost sol gel spin coating process. The suggested photodetector shows high responsivity, external quantum efficiency, detectivity, and sensitivity at specific wavelengths and light illuminations.
IEEE PHOTONICS TECHNOLOGY LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Jogendra Singh Rana, Santanu Das, Satyabrata Jit
Summary: This letter presents the fabrication and characterization of a p-type polymer (PTB7) thin film based vertical structure for white light detection application. The PTB7 thin film was deposited using a low-cost and facile floating-film transfer method. The device exhibited a maximum responsivity of approximately 146.13 mA/W and detectivity of approximately 4.137 x 10(10) Jones under a reverse bias of -2 V and white light intensity of approximately 0.228 mW/cm(2). The rise/fall time of the device was measured as approximately 0.016/0.112 s.
IEEE PHOTONICS TECHNOLOGY LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Azam Malekpoor, Seyed Amir Hashemi, Satyabrata Jit
Summary: In this article, clockless circuits for the basic logic gates, i.e. and and or gates, are designed using quantum phase slip junction (QPSJ). The proposed clockless gates remove the need for internal clock pulse synchronization, leading to reduced design complexity and smaller chip area, higher operation frequency, and lower power dissipation.
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
(2023)
Article
Engineering, Electrical & Electronic
Abhinav Pratap Singh, Satyabrata Jit
Summary: This article investigates the effect of the MoOx hole transport layer (HTL) on the performance of a photodetector fabricated on indium-tin oxide (ITO) substrates. It compares the performance of a conventional device structure with that of a proposed structure that includes the MoOx HTL to enhance hole transport and reduce dark current. The trapping of photogenerated electrons at the intrinsic defects of ZnO colloidal quantum dots (CQDs) is also explored to enhance the external quantum efficiency (EQE).
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Deep Chandra Upadhyay, Satyabrata Jit
Summary: This letter presents a metal-semiconductor-metal dual band photodetector with an interdigitated electrode structure of silver on CdSe nanocrystals-coated ZnO structure. The device exhibits dual-wavelength detection property with high responsivities and detectivities at 380 nm and 540 nm, under low bias voltages. The transient characteristics analysis reveals fast rise and fall times for both UV and visible light.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Ajay Kumar Dwivedi, Satyabrata Jit, Shweta Tripathi
Summary: This article presents an organic-inorganic broadband photodetector based on an Al/tin disulfide (SnS2)/molybdenum disulfide (MoS2)/poly(3,4-ethylene dioxythiophene) polystyrene sulfonate (PEDOT:PSS)/indium tin oxide (ITO) structure. The device demonstrates enhanced photocurrent by utilizing a built-in electric field at the heterojunction of MoS2 and SnS2. The photodetector exhibits high responsivity and external quantum efficiency, thanks to the trap-assisted photomultiplication phenomena caused by defects in the SnS2 active layer.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Ashutosh Kumar Dikshit, Srinivasa Rao Pathipati, Jogendra Singh Rana, Satyabrata Jit
Summary: Perovskite nanoplatelets (NPLs) prepared using the vacuum-assisted lowtemperature (VALT) method exhibit excellent photoluminescence (PL) properties, making them promising materials for optoelectronic applications. These NPLs, with their large surface-to-volume ratio, are capable of cutting off longer wavelength photons and have high sensitivity. By utilizing postsynthesis passivation, the PL quantum yield (PLQY) of the synthesized NPLs is boosted up to 80% and remains stable for a long period.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Franck Sabatier, Cedric Durand, Dominique Drouin, Michel Pioro-Ladriere, Fabien Ndagijimana, Philippe Galy
Summary: This study investigates the possibility of improving the quality factor and (or) inductance of an inductor integrated into CMOS technology by adding magnetic materials around it. The performance improvement is evaluated through 3D numerical simulations on an SOI substrate made in a 28 nm UTBB FDSOI technology. The choice of materials and their design topologies are the main parameters studied, leading to a solution selection based on the final application. The results show significant improvements in inductance and quality factor by using different design topologies and materials.
SOLID-STATE ELECTRONICS
(2024)
Article
Engineering, Electrical & Electronic
Tobias Reiter, Luiz Felipe Aguinsky, Francio Rodrigues, Josef Weinbub, Andreas Hoessinger, Lado Filipovic
Summary: Atomic layer processing (ALP) is a modern fabrication technique that allows precise control of film thickness, composition, and conformality at a nanometer scale. This article presents a model for surface coverage during ALD in the presence of desorption, leading to incomplete conformality. The model combines diffusion and kinetics methods and has been incorporated into topography simulators for accurate representation of reactor conditions.
SOLID-STATE ELECTRONICS
(2024)
Article
Engineering, Electrical & Electronic
Jingxuan Sun, Yi Han, Yannik Junk, Omar Concepcion, Jin-Hee Bae, Detlev Gruetzmacher, Dan Buca, Qing-Tai Zhao
Summary: This study systematically investigates the formation of NiGeSn and its contact resistivity with GeSn semiconductors. The optimal formation temperature of NiGeSn is found to be 325 degrees C, resulting in a lower contact resistivity on n-GeSn. The study also discusses the elemental diffusion mechanism during the NiGeSn formation. Additionally, GeSn exhibits low contact resistivity at 5 K, making it valuable for optimizing contact technologies for low-power and cryogenic applications.
SOLID-STATE ELECTRONICS
(2024)
Review
Engineering, Electrical & Electronic
Daniela Dragoman, Mircea Dragoman
Summary: Graphene's unique properties have led to the exploration of its analogies in various solid-state structures and systems, enabling the observation of novel phenomena and revealing differences in behavior between different systems. This review highlights the value of using analogies to develop new devices and expand our understanding of physics.
SOLID-STATE ELECTRONICS
(2024)
Article
Engineering, Electrical & Electronic
Sumreti Gupta, Asifa Amin, Reinaldo A. Vega, Abhisek Dixit
Summary: The multifrequency capacitance-voltage characteristics of high-k HfO2-based 10-nm bulk n-channel FinFETs were studied in this work. The dispersion observed in the accumulation region with respect to temperature was found to be influenced by the substrate time constant. Multifrequency conductance measurements and the variation in the surface potential quotient of the accumulation region were used to investigate the effect of direct tunneling current. Modifications to the existing accumulation region compact model equations were proposed.
SOLID-STATE ELECTRONICS
(2024)
Article
Engineering, Electrical & Electronic
N. Vasileiadis, A. Mavropoulis, I. Karafyllidis, G. Ch. Sirakoulis, P. Dimitrakis
Summary: In this work, we fabricate crossbar arrays of silicon nitride resistive memories on silicon-on-insulator substrate and utilize them to realize multi-ratioed logic circuits. The electrical characterization of the memristors shows their ability of multi-state operation with 12 distinct resistance levels. Based on a dedicated modeling and fitting procedure, a reconfigurable logic based on memristor rationed logic scheme is designed and a crossbar integration methodology is proposed. Furthermore, circuitry aspects are simulated with a calibrated model and power optimization prospects are discussed.
SOLID-STATE ELECTRONICS
(2024)
