Defect-controlled synthesis of graphene based nano-size electronic devices using in situ thermal treatment

Defect-controllable reduction approach of graphene is demonstrated. By in situ thermal reduction from graphene oxide on silicon wafer (300 nm SiO2), large size (similar to 15 mu m) of single and few-layer graphene with highly improved electrical properties has been prepared. The effects of increasing annealing temperature on reducing the defect, restoring the lattice and enhancing the field-effect performance of graphene are proved. The characteristics of the sample were analyzed using optical microscope (OM), atomic force microscope (AFM), X-ray photoelectron spectra (XPS), Raman laser, semiconductor parameter analyzer and a micromanipulator. The devices based on the obtained few-layer graphene exhibit relatively high p-type transistor characteristics (6.2 cm(2)/V s) in the atmospheric environment. (C) 2014 Elsevier B. V. All rights reserved.