On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

In this paper, we present results of a study on border trap capture/emission (C/E) process and its effect on small signal admittance of III-V devices. A MOS admittance model using a non-radiative multi-phonon phenomenon as the basis of the border trap capture/emission process is developed and utilized to investigate the effect of parameters like temperature, gate voltage, oxide thickness and trap distribution on capture/emission process. The simulation results are found to match closely with experimentally observed temperature, voltage and dielectric thickness dependencies in experimental admittance data. (C) 2015 Elsevier B.V. All rights reserved.