期刊
MICROELECTRONIC ENGINEERING
卷 145, 期 -, 页码 75-81出版社
ELSEVIER
DOI: 10.1016/j.mee.2015.03.038
关键词
Hybrid process; Chip dicing; Self-alignment; Surface activated room temperature bonding; Size-free integration; MEMS
资金
- Japan Society for the Promotion of Science (JSPS)
- Council for Science and Technology Policy (CSTP)
Wafer level chip scale package (WLCSP) is one of the most promising methods for the integration of micro-electromechanical systems (MEMS) with integrated circuits (IC). In our previous works, we have successfully developed a 2-step approach by using a carrier wafer for size-free MEMS-IC integration. This approach exhibits both excellent process flexibility and high efficiency. This approach has been proved practically valuable when compared to chip to wafer (C2W) bonding or wafer to wafer (W2W) bonding. For the improvement of above approach, the phenomenon of the chip to carrier wafer self-alignment was investigated in this work. The process parameters and the chip-dicing processes, which may affect yields and accuracy of the self-alignment, were analyzed. A hybrid process was then proposed for chip-dicing to reduce the process cost as well as to decrease the exhaust of greenhouse gases. Moreover, a surface activated room temperature bonding process was introduced and optimized for transferring of above chips from the carrier wafer to a target wafer with less damage to those chips. A full size-free MEMS-IC integration process was finally demonstrated, and then evaluated from both electrical and mechanical points-of-view. (C) 2015 Elsevier B.V. All rights reserved.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据