Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMT

This paper presents the development of a simulation model for high-voltage gallium nitride (GaN) high-electron-mobility transistors (HEMT) in a cascode structure. A method is proposed to accurately extract the device package parasitic inductance, which is of vital importance to better predict the high-frequency switching performance of the device. The simulation model is verified by a double-pulse tester, and the results match well both in terms of device switching waveform and switching energy. Based on the simulation model, an investigation of the package influence on the cascode GaN HEMT is presented, and several critical parasitic inductances are identified and verified. Finally, a detailed loss breakdown is made for a buck converter, including a comparison between hard switching and soft switching. The results indicate that the switching loss is a dominant part of the total loss under hard-switching conditions in megahertz high-frequency range and below 8 similar to 10 A operation current; therefore, soft switching is preferred to achieve high-frequency and high-efficiency operation of the high-voltage GaN HEMT.