4.7 Article

Survey of Energy-Cognizant Scheduling Techniques

期刊

出版社

IEEE COMPUTER SOC
DOI: 10.1109/TPDS.2012.20

关键词

Survey; shared resource contention; thread level scheduling; power-aware scheduling; thermal effects; asymmetric multicore processors; cooperative resource sharing

资金

  1. National Science and Engineering Research Council of Canada (NSERC) under the Strategic Project Grant program
  2. Spanish government [TIN2012-32180, ESP00C-07-20811]
  3. HIPEAC2 European Network of Excellence

向作者/读者索取更多资源

Execution time is no longer the only metric by which computational systems are judged. In fact, explicitly sacrificing raw performance in exchange for energy savings is becoming a common trend in environments ranging from large server farms attempting to minimize cooling costs to mobile devices trying to prolong battery life. Hardware designers, well aware of these trends, include capabilities like DVFS (to throttle core frequency) into almost all modern systems. However, hardware capabilities on their own are insufficient and must be paired with other logic to decide if, when, and by how much to apply energy-minimizing techniques while still meeting performance goals. One obvious choice is to place this logic into the OS scheduler. This choice is particularly attractive due to the relative simplicity, low cost, and low risk associated with modifying only the scheduler part of the OS. Herein we survey the vast field of research on energy-cognizant schedulers. We discuss scheduling techniques to perform energy-efficient computation. We further explore how the energy-cognizant scheduler's role has been extended beyond simple energy minimization to also include related issues like the avoidance of negative thermal effects as well as addressing asymmetric multicore architectures.

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