4.5 Article

A Versatile Readout System for Small to Medium Scale Gaseous and Silicon Detectors

期刊

IEEE TRANSACTIONS ON NUCLEAR SCIENCE
卷 61, 期 1, 页码 675-682

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2014.2299312

关键词

Detector front-end electronics; FPGAs; network based data acquisition systems

资金

  1. FP7/ERC Grant [258567]
  2. European Research Council (ERC) [258567] Funding Source: European Research Council (ERC)

向作者/读者索取更多资源

This paper presents the design and performance of a readout system for gaseous and silicon detectors built for the Minos nuclear physics experiment. A major constraint was to provide a multi-thousand channel, high performance readout system with low manpower effort and tight cost. This was achieved by the re-use of some earlier ASIC and front-end card (FEC) developments, the design of a new digital readout card, called the Feminos, and the use of commercial off-the-shelf components. The proposed system fully exploits the capability of the existing 72-channel AFTER chip designed for the T2K experiment and allows seamless migration to the 64-channel AGET chip, a pin-compatible evolution under production by the GET collaboration. The Feminos is a low complexity card designed to read out a FEC equipped with four AFTER chips (T2K model) or a newly assembled FEC populated with four AGET chips. The trigger clock module (TCM) is a synchronization board that allows system scaling up to 6912 channels with 24 Feminos and FECs, a commercial Gigabit Ethernet switch, and a data acquisition PC. The design of the Feminos hardware, firmware and embedded software are detailed and it is explained how high performance, rapid development and low cost were reached. System operation and data acquisition throughput scaling with multiple Feminos are investigated.

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