Implementation of EKF for Vehicle Velocities Estimation on FPGA

In order to improve the computational performance of the extended Kalman filter (EKF) for longitudinal and lateral vehicle velocities estimation, a novel scheme for the EKF implementation is proposed based on field programmable gate array (FPGA) and System on Programmable Chip (SoPC). A Nios II processor clocked at 100 MHz is embedded into the FPGA chip. The EKF is created by C/C++ program and runs in the Nios II processor. The main procedure for the EKF implementation using FPGA/SoPC technique is decomposed into three parts: system requirements analysis, hardware design, and software design. The proposed architecture offers favorable flexibility since it supports the reconfigurable hardware and reprogramming software. For the sake of increasing the computational efficiency, the single precision floating-point customized instructions and algorithm optimization are adopted. A testing platform is introduced to evaluate the functionality and the computational performance of the EKF, which includes an FPGA prototyping board and an xPC-Target system. Simulation results of standard double lane change, slalom test, and hard accelerating and braking test show that the proposed EKF implementation scheme has acceptable precision and computational efficiency.